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In recent years, Neural Networks (NNs) have become widely popular for the execution of different machine learning algorithms. Training an NN is computationally intensive since it requires numerous multiplications of matrices that represent synaptic weights. It is therefore appealing to build a hardware-based NN accelerator to gain parallelism and efficient computation. Recently, we have proposed a...
Spin Transfer Torque (STT) switching realized using a Magnetic Tunnel Junction (MTJ) device has shown great potential for low power and non-volatile storage. A prime application of MTJs is in building non-volatile Look Up Tables (LUT) used in reconfigurable logic. Such LUTs use a hybrid integration of CMOS transistors and MTJ devices. This paper discusses the reliability of STT based LUTs under transistor...
Total ionizing dose effects on transistors, fabricated in 0.18 µm CMOS technology are investigated. Radiation induced changes in NMOS and PMOS transistors parameters are discussed. Radiation induced narrow channel effect (RINCE) is demonstrated. Degree of influence of the bias conditions on the radiation response of the transistors in the given CMOS process is shown. Finally, impact of the devices...
In depth characterization of nanopores such as ion channel proteins holds great value for medical and pharmaceutical applications. In this paper, an electrochemical interface circuit (EIC) is presented that enables both readout of individual nanopores and high throughput implementation within a lab-on-CMOS array platform. The EIC was designed for an electrochemical array microsystem that would facilitate...
A low-dropout regulator (LDR) using a matching-enhanced error amplifier (ME-EA) and a multi-threshold-controlled unity-gain buffer (MTC-UGB) is proposed in this work. With the majority of transistors being high-voltage devices of the process, the regulator tolerates a high in put voltage range, which alleviates the reliability concern caused by low-voltage transistors. The ME-EA allows for tight line...
This paper presents a novel 5.5 V resilient Pulse-Triggered-Level-Shifter (PTLS) with enhanced toggling speed. This PTLS is a based on a cascoded High-Voltage (HV) level-shifters and only uses 3.3 V, near minimum size, CMOS transistors. This HV level-shifter generates both floating and a full-scale output signals and is able to operate under supplies from 2.6 V (down to 1.8 V with strategic contextual...
The current trends for greater heterogeneity in future Systems-on-Chip (SoC) do not only concern their functionality but also their timing and power aspects. The increasing diversity of timing and power supply conditions, and associated concurrently operating modes, within an SoC calls for more efficient power delivery networks (PDN) for battery operated devices. This is especially important for systems...
This paper investigates the design architectures for reliable high-yield low operating voltage non-volatile flip-flops (NVFF) for zero-leakage and instantaneously-on ultra-low power applications in scaled CMOS technologies. A reliable thin-gate oxide NVFF, integrating OxRAM current-based storing and restoring solutions is designed and analyzed in 28nm FD-SOI. The proposed class of NVFF designs has...
This paper presents a 96.6-dB-peak-SNDR and 50-kHz-bandwidth switched-capacitor delta-sigma modulator for ADC operating at 1.8 V and consuming 7.9 mW. This performance is achieved by the introduction of Class-AB single-stage switched variable-mirror amplifiers (VMAs) combined with an optimized architecture and a 5-phase switched-capacitor scheme. The resulting 1.8-mm2 delta-sigma modulator is integrated...
The performance of priority encoder circuits is usually limited by the delay associated with the propagation of the priority token, however, proper design in the architectural level can reduce the delay stages to the order of O(log n). Furthermore, power dissipation and area pose an increasingly important concern in modern circuit design, thus the development of suitable techniques is essential. This...
To realize a high-density spin-transfer-torque magnetic random access memory (STT-MRAM) device comparable with a current dynamic random access memory (DRAM) device, it is a key to develop a new technology for memory cell size reduction. We have already reported a chemical- mechanical-polishing(CMP)-based preparation technology for magnetic tunnel junctions (MTJs) above the via holes that can drastically...
The main direction in the development of modern microelectronics is the improvement characteristics of electronic element base in the condition of the high temperature. The method of periodically doped channel is regarded as an application for transistor structures based on organic semiconductors. The possibility of channel conductivity modulation in CMOS transistors, however, is of high interest...
A new fully integrated 0.25-µm CMOS complementary LC VCO with buffer with low phase noise, wide tuning range, and high frequency of merit is reported. The developed VCO achieves a 25% tuning range across 4.6–5.9 GHz, phase noise of −117 dBc/Hz at 1-MHz offset, and frequency of merit of 183.7. The integrated VCO has a die size of 320µm×300µm.
Multiport CMOS cell with the soft-error immunity based on DICE which is divided into two spaced groups of transistors each of them consisting of four transistors. The larger the distance between these two CMOS transistor groups, a multiport SRAM is more hardened to single event upsets. The result of a single nuclear particle strike only on the one transistor group of a DICE trigger is a single-event...
Researchers have predicted the end of the Moore law. One of the reasons is that MOS bulk transistor is reaching its limits: Sub-threshold Slope (SS), Drain Induced Barrier Lowering (DIBL), Threshold Voltage (Vth) and Vdd scaling slowing down, more power dissipation, less speed gain, less accuracy, variability and reliability issues. Up to now, the industrial solutions focus on silicon CMOS technology...
A 14-bit 2.5-GS/s current-steering digital-to-analog converter (DAC) was designed in a 55-nm CMOS technology. For such a high sampling rate, time-relaxed interleaving digital random return-to-zero (TRI-DRRZ) is an effective method to improve the dynamic performance of the DAC by randomizing the switch glitches. A useful technique called CAL-TRZ is proposed in this paper. It combines TRI-DRRZ with...
Electromagnetic compatibility (EMC) is an essential requirement to electronic systems in which integrated circuits have a major influence. Intrinsic degradation mechanisms, which produces anticipated wear-out in deep submicron components threat not only the reliability of circuits, but also EMC performances. The need to predict and ensure long-term EMC has become a key challenge. This paper aims at...
The impact of the emitter polysilicon etching in Tetramethyl Ammonium Hydroxide (TMAH) on the characteristics of high-linearity mixers fabricated with the low-cost Horizontal Current Bipolar Transistor (HCBT) is analyzed. During emitter formation, the thick layer of α-Si is deposited over the whole wafer, which is then etched-back in the TMAH. The emitter thickness depends on the TMAH etching time...
This paper presents the design of a power amplifier integrated in a CMOS 180 nm technology, which is intended to drive an inductive link operating at 990 MHz. A class-D topology is employed to avoid the use of inductors. A design methodology is proposed to find the optimal transistor width, solving the trade-off between the ON-resistance and gate capacitance. The area occupied is 1.5 mm2, most of...
This work proposes a strategy for designing VLSI circuits to operate in an extremely wide Voltage-Frequency Scaling (VFS) range, from the supply voltage at which the minimum energy per operation (M EP) is achieved, up to the nominal voltage for the process. First the sizing methodology of two library cells using transistors with different threshold voltages: Regular-VT (RVT) and Low-VT (LVT) is described...
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