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In this paper, a new analytical model for describing the output waveform of the CMOS inverter for planar and FinFET nanoscale technologies, is introduced. A modified expression for the transistor current is adopted taken into account nano-scale effects like DIBL, CLM and NWE. The sub-threshold current of both transistors as well as their drain-to-bulk capacitances, which influence significantly the...
In this work, a low-voltage implementation for continuous-time ΣΔ analog-to-digital converters is proposed. The low-voltage implementation technique is based on implementing the sigma delta integrators using CMOS inverters. The proposed technique is applied to a third-order single loop modulator. The first integrator in the loop filter is an active RC integrator, while the remaining integrators are...
Adiabatic switching techniques based on energy recovery principle are one of the best solutions at circuit and logic level to achieve reduction in power. The main objective of this paper is Low Power Multiplexer design using diode free adiabatic logic and implementation of this logic into barrel shifter. A barrel shifter is a digital circuit that can shift a data word by a specified number of bits...
Low power microelectronics has become more intense and low power VLSI systems having emerged as greatly in demand. For increasing number of portable applications require small area low power high throughput. High speed high throughput, small silicon area and at the same time low power consumption is the motivation behind this. This paper presents an effective approach of constant delay (CD) logic...
This paper presents the design of a noble 24 nm asymmetric Dual gate Material (for NMOS/PMOS) Independent Double Gate (DMIDG) with elevated S/D Structure, Buried Polysilicon Back Gate, High-K dielectric spacer, High-K gate stack of HfO2 over SiO2 thin layer (SiO2 thickness being 0.85 nm while maintaining an EOT of 1.2 nm) at front gate in order to suppress SCE's. An IDG MOS device with metallic gate...
Technology evolution brings new challenges to integrated circuits (IC) design. Parameter variation and complex design rules demand a great effort to create suitable design approaches to ensure manufacturability. Regular layout techniques allow a more accurate estimate of the circuit power and delay in early design steps. In this context, this work presents an evaluation of a set of basic cells candidates...
Analog-to-Digital converters (ADC) are useful components in signal processing and communication systems. In the digital signal processing (DSP) low power and low voltage are of prime concern and it is challenging to design high speed mixed signal circuits. This paper describes the ultra high speed ADC design using a 2×1 multiplexer based encoder that is highly suitable and accurate. Speed is an important...
This paper presents a low power D-latch designed using two low power tri-state MCML buffers. The proposed D-latch consumes less power as it makes use of low power tri-state buffers which promotes power saving due to reduction in the overall current flow in the circuit during the high impedance state. The proposed low power D-latch is simulated in PSPICE using 0.18μm TSMC CMOS technology parameters...
Carbon Nanotube Field Effect Transistor (CNFET) is best alternative to design SRAM cell in submicron range because of its excellent electrical properties, high stability, high Performance and low power dissipation in submicron range. This paper proposes a design of 6T SRAM cell based on 32nm CNFET considering nanotube diameter and transistor sizing. By using proper transistor sizing the SRAM cell...
In this work, a novel design paradigm for an ultra-low power and area efficient CMOS Flash ADC has been introduced. New techniques such as dual mode operation and use of sized threshold voltage are employed to reduce both static and dynamic power exponentially. Architectural improvements are adopted both at the macro and micro design level, such as the TIQ (Threshold Inverter Quantizer) structure...
Gate-all-around (GAA) metal-oxide-semiconductor field-effect transistors (MOSFETs) are high priority research topics of the present day. The ability to increase the drive current through a multi-channel (MC) architecture is a unique feature in GAA devices. Limitations in the fabrication process may result in non-circular cross-section of GAA MOSFETs. The most practical approach is the elliptical cross-section...
Wireless device portability and power efficiency are the two major challenges in modern device modeling. Voltage Controlled Oscillator (VCO) is one the most essential circuit used in wireless systems. A new three stage VCO design in 65nm technology is proposed in this paper and is compared with previous best Current starved VCO design on the basis of on-chip area utilization and power consumption...
In this paper, an approach for modeling the output waveform and the propagation delay of the CMOS inverter in nanometer technologies is introduced. An initial output waveform is calculated by solving the corresponding differential equations of the circuit only for the conducting transistor. The effect of the short-circuit current is treated as an additional charge that has to be discharged through...
Time-based ADC is an essential block in designing software radio receivers because it exhibits higher speed and lower power compared to the conventional ADC, especially, at scaled CMOS technologies. In time-based ADCs, the input voltage is first converted to a pulse delay time by using a Voltage-to-Time Converter (VTC) circuit, and then the pulse delay time is converted to a digital word by using...
In this paper, an on-chip all digital temperature sensor using dual ring oscillators which have different gate channel length is proposed for maintaining the performance benefit of CMOS digital circuit. This novel temperature sensor measures the temperature variations between the temperature-sensitive ring-oscillator and the temperature-insensitive ring-oscillator according to temperature. The sensitivity...
Digital threshold detection is a fundamental logic function that is heavily utilized in a large family of arithmetic processors and neural networks. While recently proposed capacitive threshold logic (CTL) design technology promises to offer a compact and effective solution to threshold detection, its potential to scale to different problem sizes was not previously quantified as compared to traditional...
CMOS based technologies fail to satisfy the Moore's law beyond Nano scale, leading to intensive research in identifying an alternative technology that can take over CMOS in the near future. Quantum Dot Cellular Automata (QCA) is one among the various technologies proposed by the International Technology Roadmap for Semiconductors (ITRS) as a viable alternative to CMOS. QCA offers the highest device...
In CMOS technology, NMOS- and PM0S-FETs are hardware defined by choosing the appropriate doping of source (S) and drain (D) junctions with respect to the substrate. However, in this work we report on a novel CMOS multi-gate (MG) nanowire field-effect transistor (NWFET) architecture on silicon-on-insulator (SOI) material which is virtually free of doping. The MG-NWFETs are originally ambipolar nanowire...
The performance of modern integrated circuits is significantly influenced by coupling effects of interconnects. Crosstalk noise must therefore be analyzed in the early stage of design to develop reliable VLSI interconnects. In this paper, we present a closed form crosstalk noise estimation technique to coupled RLC interconnects based on coupled transmission line theory and Fourier series analysis...
We demonstrate for the first time a dense co-integration of co-planar nano-scaled SiGe p-FETs and InGaAs n-FETs. This result is based on hybrid substrates containing extremely-thin SiGe and InGaAs layers on insulators (ETXOI). We first show that such hybrid substrates can be fabricated by direct wafer bonding with stacked high-mobility layers thinner than 8nm. A process flow is presented that allows...
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