The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
By realizing a high-quality epitaxial La2O3/ GaAs(111)A interface, we demonstrate GaAs CMOS devices and integrated circuits including nMOSFETs, pMOSFETs, CMOS inverters, NAND and NOR logic gates and five-stage ring oscillators for the first time. As an exercise of III–V CMOS circuits on a common substrate with a common gate dielectric, it provides a route to realize ultimate high-mobility CMOS on...
This paper presents a 2.4 GHz low-power CMOS On-Off Keying receiver front-end which contains a low noise amplifier with a novel down conversion mixer that is designed for wireless forward telemetry link in neural stimulation applications. The transceiver operates between 2.4 and 2.5 GHz to support the full industrial, scientific and medical band. The post-layout simulation results show that the fully...
We present a new method to phase-modulate RF pulses through injection locking. The modulator can produce BPSK or QPSK modulated pulses over a frequency span of 3 to 10 GHz. The RF pulses are produced using a fast on/off switching technique to power up and power down a tunable ring oscillator. Experiments show that the modulator's energy consumption ranges from 13 pJ/pulse to 18 pJ/pulse as the carrier...
This paper presents an accurate analytical delay model for CMOS inverter considering both subthreshold and superthreshold operating regions. Previous related work are either only valid for a specific operating condition or assume a step input. Therefore, that is the first approach to consider both different operating regions and input transition time. Moreover, the proposed model also considers several...
A Freeze Vernier delay line time-to-digital converter for very low power and high resolution is presented. The Freeze Vernier Delay Line is a Vernier-type TDC, where the state of the start line can be frozen by the stop line, omitting the power-hungry time capture elements like D-registers or arbiters that are usually employed in a Vernier TDC. The two main issues of the design, the charge kickback...
We present in this paper the design of a wide-band efficiency-enhanced CMOS rectifier. A novel semi-active diode is proposed to minimize both the diode forward voltage drop and the reverse leakage current. This is achieved by dynamically configuring the rectification device as a threshold compensated diode in the on-state while a standard MOS diode in the offstate, respectively. The proposed rectifier...
Our previously proposed ultra low-power subthreshold adiabatic logic has been a problem that noise margin is reduced, so that it is impossible to implement a cascade connection. In this paper, we propose a novel sub-threshold adiabatic logic. To evaluate our proposed circuit, a half adder, full adder, dynamic flip flop and 4×4 array multiplier are designed, and then the operation function and power...
A 1.1 um pitch pixel array fabricated by 45 nm 3D stacked technology, can be switched to peripheral circuits on same wafer or to other stacked wafer for process and signal integrity verification. It supports through silicon connection or direct connection to increase the flexibility by separating pixel array and sensing circuit. The novel wide operation range VCO and low power serializer are implemented...
This paper presents an energy efficient inverter based readout circuit for implantable pressure bridge piezo-resistive sensor which can achieve 9 bit resolution with 28.8-mV input voltage range. Only one bridge branch is utilized with interchanging supply voltage to achieve net differential input voltage range, hence reducing the power consumption by a half. A gain compensated technique is applied...
This paper describes CMOS time-domain temperature sensors. A principle of this type of sensors is CMOS inverter's time-delay variation with temperature. The variation, however, has nonlinearity which is a fundamental error source. Therefore, we propose a new temperature sensor that improves linearity using an injection-locked oscillator (ILO). Since the ILO has the opposite curvature of an inverter...
A CMOS analog circuit topology is presented that provides a number of stable operating points based on a laddered inverter quantizer (LIQAF) circuit. An input voltage sets the initial voltage state value when a CMOS transmission gate is turned on, and the voltage state then settles to the nearest stable operating point once the CMOS transmission gate is turned off. The proposed analog circuit achieves...
An ultimate CMOS structure composed of high mobility wire channel InGaAs-OI nMOSFETs and SGOI pMOSFETs has been successfully fabricated by means of sequential 3D integration. Well behaved CMOS inverters and first demonstration of InGaAs/SiGe (Ge) dual channel CMOS ring oscillators are reported. The 21-stage CMOS ring oscillator operation was achieved at Vdd as low as 0.37 V with the help of adaptive...
We demonstrate the first VLSI-compatible approach for monolithic three-dimensional (3D) integration of carbon nanotube field effect transistors (CNFETs) with silicon CMOS for high-performance digital logic applications. Fine-grained monolithic 3D integration is demonstrated at the logic gate level, whereby individual logic gates are composed of both CNFETs and silicon FETs. Monolithic 3D integration...
A novel fully complementary and fully differential open-loop comparator topology, that consists of a two-stage preamplifier cascaded with a latch, achieves a sub-100 ps propagation delay for a 50 mVpp input signal amplitude under 1.1V supply and 2.1mW power consumption. The comparator features two differential pairs of inputs and is truly self-biased through a negative feedback loop thereby eliminating...
In this work an inverted-based low-voltage implementation for continuous-time sigma delta analog-to-digital converters is proposed. The proposed implementation is applied to a third-order single loop modulator. The loop filter is implemented using active RC integrators. A 50 dB SNDR is achieved for a signal bandwidth of 2 MHz and sampling frequency of 100 MHz, while consuming 1 mA from 0.75 V, supply...
Estimating the failure probability of nano-scale generic logic cells is a key point for the evaluation of digital system reliability. Noise-induced input variations with process-induced threshold voltage variations affect the probability of correct operation of logic cells. This work quantitatively analyses the probability of invalid output of a cell by introducing novel analytical and semi-analytical...
A 4-bit flash analog to digital converter with high speed, low power, and small area for system on chip(SoC) applications is presented. The proposed ADC is designed with BSIM4 90nm CMOS technology and 1.2V power supply. In comparison to the conventional analog comparators, it uses Threshold Inverter Quantization technique to generate comparators. The replacement results in a faster digital conversion...
Silicon technology continues to scale down and is a dominant choice for high-performance digital circuits. For enhancement of digital circuit performance researchers are further investigating other novel materials to introduce into future technology generations. Carbon nanotubes (CNTs) have been explored as a promising candidate for the same due to their excellent carrier mobility. The effect of CNTFET...
Computers transform to the smaller, faster and more reliable devices year by year. Accordingly designing more efficient logic gates, as the basic blocks of the VLSI chips, are essential for circuit designers. Since the integration reached to its limits through the conventional technologies mainly the CMOS based VLSI designs the quest for the novel promising technologies was commenced. Memristor is...
In this paper, we propose a test method for detecting pin opens of CMOS logic ICs in assembled PCBs. The test method is based on supply current of a circuit under test which flows when a time-varying signal is provided to a targeted pin with a test probe as a stimulus. Test signal's amplitude is less than VDD. Test vector generations are not needed for the tests. In the test, the test probe also can...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.