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This paper deals with the diagnosis of the electrical faults of induction motor operating under the direct field-oriented control. Two different faults are taken into account: stator winding inter-turn short circuit and voltage source inverter transistor damage. The fault diagnostic algorithms are described. Performance of both algorithms is validated in presence of the different kind of damages....
This paper presents a comparative analysis of the energy characteristics of two topologies multilevel semiconductor converters: a three-level voltage source inverter and two-zone current source inverter. Computer simulation was used to obtain energy and control characteristics of studied converters. Harmonic distortion was used as the primary evaluation criteria to compare the quality of output voltage,...
This paper presents the design of digital logic cells for subthreshold applications using 28 nm ultra-thin body and box fully depleted silicon on insulator technology. The sizing approach relies on balancing pull-up/pull-down networks (PUN/PDN) strength ratio by applying an additional forward back-gate biasing (FBB) voltage to the back-gate of PMOS transistors. The minimum width of PMOS and NMOS transistors...
One of the reasons for deterioration of the efficiency of operation of a variable-frequency electric drive (VFED) with scalar control consists in occurrence of asymmetry of induction motor (IM) parameters. Apart from appearance of variable components of consumed power and electromagnetic torque, such asymmetry causes deterioration of operating mode of an autonomous voltage inverter (AVI). Assessment...
This paper presents Adomian Decomposition based analysis of regeneration time constant of CMOS dynamic cross-coupled latch. A CMOS dynamic cross-coupled latch, which is a nonlinear system, is typically analyzed by linearizing it around an operating point to arrive at regeneration time constant. However, the time domain behavior obtained using the linear analysis deviates from the actual behavior of...
As Design Complexity is growing and Size of the individual components i.e mosfets shrinks, it led to the need for increased clock speeds, to do faster computation and propagate the clock to different subsystems of the chip. The clock to be routed must be free from clock skew and jitter. The alternate method for reducing power requirement is use of multi-Vdd i.e more than one supply voltage depending...
This paper proposes a fully Digital, Analog-to-Digital Converter (FD-ADC) which is designed by using UMC's 180 nm digital CMOS technology. The advantages of the digital ADC are its simplicity and low complexity. Power dissipation is also very less compared to other ADC architectures. The FD-ADC is suitable for low power applications and where the input signal swing is small. FD-ADC also needs very...
In comparison with conventional operational amplifier, ring amplifier can achieve better power efficiency for switched capacitor circuits. However, the cascade-inverter architecture of ring amplifier may suffer from undesirable oscillation which has a great impact on transient stability. This paper presents a latched-based ring amplifier which is capable of decreasing the probability of oscillation...
This paper deals with a Sub-Hexagonal Centre PWM (SHCPWM) with variable switching sequence for a topology based on cascaded connection of two converters, so called dual inverter. The SHCPWM is enhanced to consider the last IGBT switching state representing the previous space vector and to balance and reduce power losses among the transistors. The proposed method is compared with the known SHCPWM with...
Printed/Organic Electronics (PE) is an emerging technology with gargantuan market potential, particularly if its realization is low cost and the supply chain associated with its design is manageable/established. For the former, a Fully-Additive All-Air Low-Temperature process (vis-à-vis a Subtractive process) is desirable, while for the latter, a comprehensive Process Development Kit (PDK) for Electronic...
Memristors have emerged as promising, area-efficient, nano-scale devices for implementing models of synaptic plasticity in hybrid CMOS-memristor neuromorphic architectures. These architectures aim at reproducing the learning capabilities of biological networks by emulating the complex dynamics of biological neurons and synapses. However, to maximize the density of these elements in crossbar arrays,...
This paper presents an adaptive ring amplifier that introduces a degree of freedom in speed/stabilization design trade-off in the original ring amplifier. It also introduces an area efficient solution for the auto-zeroing stability problem that the conventional ring amplifier suffers from. The proposed adaptive ring amplifier improves the linearity by 10dB at the same opera ting frequency. Moreover,...
The acceleration sensitivity and its related problem of force-frequency in quartz resonators were studied. We studied the effects of initial nonlinear strains versus the effects of nonlinear elastic constants on the force-frequency problem of quartz resonators subjected to bending forces. We found that for quartz thickness shear resonators subjected to bending, the force frequency effect could be...
In this paper, we present a VCO designed for operation at 250 mV dissipating 590 nW, free running frequency of 462 kHz with voltage-to-frequency maximum non-linearity of 0.33%. The VCO design aim to a time based ADC, whose resolution is highly limited by the non-linearity of the VCO itself, which may be corrected by further digital calibration. The proposed VCO uses a ring oscillator topology and...
Multiport CMOS cell with the soft-error immunity based on DICE which is divided into two spaced groups of transistors each of them consisting of four transistors. The larger the distance between these two CMOS transistor groups, a multiport SRAM is more hardened to single event upsets. The result of a single nuclear particle strike only on the one transistor group of a DICE trigger is a single-event...
Researchers have predicted the end of the Moore law. One of the reasons is that MOS bulk transistor is reaching its limits: Sub-threshold Slope (SS), Drain Induced Barrier Lowering (DIBL), Threshold Voltage (Vth) and Vdd scaling slowing down, more power dissipation, less speed gain, less accuracy, variability and reliability issues. Up to now, the industrial solutions focus on silicon CMOS technology...
Despite of remarkable technological achievements reached in power electronics (both for devices and circuits) faults remains inevitable, being the main cause of power systems interrupts and failures. In the last decade the fault problem in power electronics has been investigated with more attention both from theoretical and experimental point of view. Following these trends, this paper is focused...
Photovoltaic systems are a widespread form of green energy, that is becoming increasingly considered also as a form of economical investment. Their reliability is consequently becoming a concern. In this paper we focus on the reliability of the DC-AC converters (inverters) of photovoltaic (PV) systems. We analyze the effects of the faults likely to affect their operation in the field. We show that...
We present MUX based programmable logic circuits built from newly proposed compact and efficient designs of combinational logic gate. These are enabled by reconfigurable Schottky barrier nanowire transistors with multiple independent gates, which can be dynamically switched between p- and n-type functionality. It will be shown that a single device can be used to replace paths of several transistors...
Nowadays, the Leakage power is one of the major issue for CMOS circuit on nanometer technology. And it is increases as the process technology become finer and finer with device density increases. As the supply voltage lower down, gate oxide thickness have to reduce to reduce the threshold voltage which helps in maintaining the performance. But there is significant increase in leakage power dissipation...
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