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This paper presents a high speed Radix-8 Log-MAP turbo decoder recursion architecture: algorithmic approximation and architectural optimization are incorporated in the proposed designs to reduce the critical path. The synthesis results show that the proposed design has a high throughput of 693 Mbps in 0.18 um CMOS technology, which is nearly 3 times higher than using conventional Radix-2 architecture...
This paper introduces a parabolic synthesis methodology for developing approximations of unary functions like trigonometric functions and logarithms which are specialized for efficient hardware mapped VLSI design. The advantages with the methodology are, short critical path, fast computation and high throughput enabled by a high degree of architectural parallelism. The feasibility of the methodology...
Salsa20 is a stream cipher candidate in the software-oriented profile of the eSTREAM project. ChaCha is a successor stream cipher with improved per round diffusion and, conjecturally, increased resistance to cryptanalysis. Based on the combination of four Salsa20 instances, Rumba is a compression function for hashing schemes. This paper presents the evaluation of five VLSI circuits for Salsa20. Synthesis...
This paper presents a research to strengthen the using of embedded system memory, including: Flash memory, SRAM, DRAM etc. For increasing the reliability on data storage, we use the conventional fault-tolerant mechanisms-Mirror and CRC techniques to carry out the forward protection at first. Furthermore we use the encryption and Reed-Solomon code to improve the function at back end. This article designs...
Advances in the VLSI technology have provided designers with significant impetus for porting algorithm into architecture. In this paper, we propose an architecture with low latency for the implementation of CORDIC algorithm in rotation mode suited for parallel and pipelined operation. In our proposed architecture, redundant radix-4 arithmetic is employed to reduce iteration delay and halve the number...
This paper proposes an AES algorithm against both differential power analysis and differential fault analysis and its hardware implementation. This new algorithm emphasizes the feature of defending hardware against two kinds of side-channel attack simultaneously. Since the modified AES algorithm is much more complex than the original one, this paper exploits low hardware cost architecture to realize...
With the growing number of video content analysis applications, efficient implementation has become increasingly important. Video-object tracking using image moments is an important subtask in video-content analysis content algorithms. In this paper, we will present a method of accelerating the computation of geometrical moments and the resulting moment engine to a throughput of 130-fps. Furthermore,...
Recently, the growing numbers of cryptosystems based on chaos have been proposed; many of them have good statistical properties and security but low efficiency. To increase operating efficiency of cryptosystems, an improved chaos-based stream cipher algorithm based on discrete chaotic maps is presented. The algorithm improves the complexity of chaos by randomly changing chaotic control parameter....
On the problem that the hardware overhead of hardware implementation architecture for discrete wavelet transform wastes a lot, on the basis of flipping structure, we propose a high performance hardware implementation architecture. The architecture merges the lifting step and adopts the pipelined design to adjust the primitive data path. The proposed 2-D DWT architecture consists of four parts: column...
In this paper, the design of VLSI sorter architecture for the acceleration of data sorting operation is addressed. In order to support the sorting of the variable length sequences, the sorter architecture discussed in this paper is based on a central memory module equipped with some fundamental compare-and-swap (C&S) functional units. Three memory-based sorter designs have been addressed. In addition...
This paper presents an efficient implementation of a convolution-based 1D discrete wavelet transform (DWT). The proposed architecture combines several optimizations that improve the performance of the hardware design in terms of throughput and power dissipation. We designed and analyzed the performance of numerous DWT architectures using pertinent metrics and cost functions that assess the impact...
This paper presents a novel image interpolation method, extended linear interpolation, which is a low-cost architecture with the interpolation quality compatible to that of bi-cubic convolution interpolation. The architecture of reducing the computational complexity of generating weighting coefficients is proposed. Based on the approach, the low-cost hardware architecture with digital image scaling...
Variable block sizes, complex spatial motion vector prediction, particular skip and direct temporal MV prediction contribute to superior performance of H.264 standard. However, high irregularity of its MV prediction algorithm also makes efficient hardware implementation challenging. In this paper, an efficient VLSI architecture is proposed for irregular MV prediction implementation. Complex control...
In this paper, two hardware-oriented fast motion estimation algorithms and their implementations into a 2D systolic array for variable block size motion estimation architecture are presented. Two hardware oriented algorithms are proposed to increase the coding speed and reduce the computation complexity of the fast motion estimation (FME) algorithm. The results show that the proposed FME algorithm...
Systolic array is a well known VLSI architecture to achieve extensive parallel and pipelining computing. Many systolic designs have been reported. All are algorithm based, that is one design is only for solving one specific problem. In this paper, the special purpose systolic architecture has been extended into a reconfigurable one and a systematic design approach to mapping two or more algorithms...
Intra coding in H.264/AVC has significantly enhanced the video compression efficiency. However, computation complexity increases due to the rate-distortion (RD) based mode decision. This paper proposes a new fast mode decision algorithm in H.264/AVC intra prediction and its VLSI architecture. A new edge-detection pattern is proposed and both edge-detection technique and spatial mode prediction technique...
The paper deals through computer-aided modeling, numerical simulation and experimental research with the bio-inspired digital systems, in order to implement VLSI hardware which exhibits the abilities of living organisms, such as: evolution capabilities, self-healing and fault-tolerance. The theoretical backgrounds of the work are founded in cellular embryology's basic concepts. In the first stage...
Bio-inspired hardware systems computer-aided modeling, simulation and experimental research are presented in the paper, with the purpose to design and experiment digital systems with abilities of biological organisms. Original model for an FPGA-based artificial cell provided also with strongly network communication behaviors and fault-tolerant operation mode is proposed and developed. The complex...
This paper presents a high-precision algorithm for the forward and inverse MDCT computations using the unified recursive architecture. In this algorithm, the kernel transform of MDCT/IMDCT can share the same architecture because the coefficients for the recursive formula are the same. The preprocessed input samples in the proposed algorithm allow a lower dynamic range than those of other recursive...
A systolic-like modular architecture is presented for hardware-efficient implementation of two-dimensional (2-D) discrete wavelet transform (DWT). The overall computation is decomposed into two distinct stages; where column processing is performed in stage-1, while row processing is performed in stage-2. Using a new data-access scheme and a novel folding technique, the computation of both the stages...
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