The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
With the technology nodes keep advancing, the application of TSV(Through Silicon Via) technology in 3D integration is faced with more challenges. The shift from via-last to via-middle fabrication scheme, the ever-increasing density of TSV, the reduction in supply voltage and the increase in frequency of on-chip local clock, all pose threat to signal/power integrity of the TSV system. In this paper,...
The estimation of dependable noise margins in digital cells is increasingly significant as nano-scale CMOS technology is facing true reliability issues. On one hand, a major concern comes from circuit aging mechanisms, such as NBTI, which degrade the reliability of circuit operation over time. On the other hand, variability in technology parameters results in affecting reliability. The impact of such...
A novel sequential inter-stage correlated double sampling technique has been proposed. This technique provides considerable enhancement in the effective accuracy of a switched-capacitor architecture. Superior accuracy and thermal noise performance is achieved compared to the conventional correlated double sampling technique. The proposed approach provides higher input signal bandwidth by reducing...
Total voltage sources and Thevenin equivalent circuits are derived by measurements and simulations using IBIS models to characterize the conducted emissions from ICs. The constructed noise source model for a test IC is applied in systemlevel simulations and the calculated far field radiation is validated with measurements. The agreement between simulated and measured results demonstrates the effectiveness...
This paper discusses the design of high-speed low-power decimation filter for wideband Delta-Sigma ADC. It presents a low power decimation filter with programmable decimation ratios (32, 64 and 128) and sampling rates (624MHz, 312MHz and 208MHz) for LTE application. The decimation filter has five different operating modes and consists of three sinc filters, two halfband filters and a FIR filter. It...
This paper presents a SAR ADC for biomedical application, which has a strict limit on its power consumption. Thus, two techniques are introduced into its design: a novel ladder-based reconfigurable time domain (RTD) comparator is proposed to reduce the noise and to adjust power according to inputs automatically; and a novel clock distribution circuit is utilized to save more than 55% power consumption...
The paper describes the mechanism of Agilent 3458A sampling time jitter present when external triggering is used at synchronous two channel sampling. Based on measurements it is shown that the master DMM adds approximately 3.2 ns of its own time jitter while triggering the slave DMM and that the effective time jitter for externally triggered DMM remains at 7 ns, well below ±50 ns maximum jitter as...
An improved framework of power integrity analysis for core logic timing analysis is presented in this paper. Due to ever increasing power consumption of core digital blocks, jitter due to supply noise contributes a significant timing error, and on-chip logic timing analysis requires accurate modeling of supply noise induced jitter. Jitter information provides additional information to define precise...
Memory bandwidth requirements for future high-end applications such as graphics, 200G/400G networking and high performance computing is driving the need for more “on-chip memory”. Silicon Interposer based 2.5D integration provides an intermediate path to achieving high memory bandwidth by integrating memory in package. This paper discusses timing budget analysis for realizing wide IO memory interfaces...
Effects of transmit jitter on lossy clock channel are analyzed analytically by treating the 1010 input clock signal as a sinusoidal wave with a phase modulation that represents jitter. Jitter-to-amplitude-modulation transfer functions are derived for sinusoidal jitter and random jitter in terms of the signal transfer function or S-parameters. Input jitter is shown to induce amplitude modulation in...
Although decreasing IC feature size and increasing I/O speed enable better system capability and performance, they also introduce technological challenges. One of the most important challenges is as I/O speed increases: jitter should decrease accordingly to ensure a reasonable bit error rate (BER) for a link system. Precise jitter characterization of signals at critical internal nodes provides valuable...
In the design process of mixed-signal circuit, it is sometimes inevitable to meet partition of reference plane or slots on reference plane for the insulation of noise caused by different voltage level or IC's different noise susceptibility. This paper studies the undesired signal integrity problems caused by single-ended signal references on this kind of non-ideal ground plane. Firstly, a typical...
A new flip-flop design, called a duration-observation master-slave flip-flop, is proposed and evaluated. This dependable design takes into account a noise pulse induced on data signal lines. If the noise pulse occurs around the data-sampling time (i.e., clock edge), the conventional master-slave flip-flop samples an erroneous value and holds it because the flip-flop regards the noise pulse as a proper...
A modified low-power switched-capacitor integrator is proposed. It reduces power dissipation without increasing the thermal noise. The proposed integrator is parasitic-insensitive and allows a high linearity. A modified low-distortion self-coupled Delta-Sigma (Δ£) Analog-to-Digital Converter (ADC) is proposed to incorporate this new integrator. Analysis and simulations show that the high linearity...
This paper describes the implementation of a SPI-programmable clock delay chip based on a Delay Locked Loop (DLL) to be used in the upgrade of the data acquisition electronics of the upgrade of the LHCb calorimeters. in order to shift the phase of the clock (25 ns) in steps of 1ns, with a 55ps jitter and 21.5ps of delay line linearity. The delay lines will be integrated into ICECAL, the LHCb calorimeter...
We present a fully-digital digital-to-analog converter (FD DAC) architecture design for high-speed communication systems. The FD DAC design is based on the ΔΣ modulation. The specifications for the DAC includes a low 1.2 V supply voltage, a high 5 GS/s input sampling rate, and a wide 2.5 GHz bandwidth. We employ a combination of the time-interleaving, parallel, and pipelining techniques to reduce...
A sensor system for measuring the power-ground (PG) noise in very large scale integrated circuits is presented. The proposed system utilizes sensor elements with standard cell dimensions enabling high spatial resolution voltage measurements of power and ground rails. Asynchronous sub-sampling is used to directly convert the analog signals into the digital domain inside the sensors to ensure precise...
This study proposes a Spread Spectrum Clock Generator (SSCG) for Serial-ATA II, which is realized by a delta-sigma fractional-N frequency synthesizer with a digital triangular profile generator without external clock and a half-integer divider. By adding only a negative-edge-triggered resampler and using phase combination technique, the half-integer divider can be realized by any kind of integer programmable...
This paper presents a multi-bit, continuous time delta-sigma modulator with 20 MHz bandwidth implemented in 65nm CMOS for cellular communication. The modulator features a third order, single loop filter and a 4-bit internal quantizer operating at 640 MHz. The DACs are resistive for lower thermal noise compared to the current-steering DACs and nonreturn-to-zero DAC pulse is used to reduce the clock...
The area efficiency of an inductive-coupling interface is improved by 12 times for WIO2 standard (352Gb/s) and beyond. By using a quadrature phase division multiplexing, coils are overlapped and the density is increased by 4 times. It is further increased by 3 times by shortening communication distance with an ultra-thin fan-out wafer level package. The proposed DRAM/SoC interface at 356Gb/s outperforms...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.