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Variations in the power-distribution network are exacerbated because of scaled supply voltages and smaller noise margins in sub-nanometer designs, which adversely affect performance and yield. Power-Supply noise incurred by excessive simultaneous switching of multiple paths negatively impacts the timing of a circuit. Supply noise is a major issue especially during transition and delay test where test...
Clock jitter is a crucial factor in high speed and high performance application. Traditional jitter measurement method relies on precise and expensive instrumentations. This paper proposes a low cost jitter measurement and separation method. Instead of using traditional time internal analysis equipment, a simple Analog-to-Digital Converter (ADC) is used as the jitter measurement device. The clock...
This paper presents a sub-1V dynamic comparator with cross-coupled latches at multi-GHz operation. The low-voltage cross-coupled latches structure with a separated tail current can be used to optimize the speed and the offset in the latched stage, respectively. A high speed readout circuit is also proposed to further enhance the speed of the comparator. With BER=109, the comparator achieves 143fJ...
Ranging signals in the urban environment suffer from significant attenuation and additive errors caused by reflections. Special design considerations for ranging-based positioning systems that operate in the Urban Canyon are presented. The tradeoff between acquisition sensitivity and acquisition time is presented. The integrity of the measurements is improved by verifying that the signals exhibit...
We make the case that TDF timing tests, even when aggressively applied at-speed, uniquely detect mostly open defects within standard cells. The majority of these defects can also be detected at somewhat slower test speeds without the risk of unnecessary yield loss from test noise. Meanwhile, many other opens that can cause operational failures remain undetected by current LOC, and even LOS, TDF tests...
Ring PLLs play an important role in mobile baseband applications. In cases where fine frequency resolution and low jitter are both needed, wideband fractional-N PLL architectures with quantization noise (Q-noise) cancellation are preferred. Phase interpolators (PI) are widely used in recent literature [1-3]. Although the Q-noise is reduced, decreasing supply voltages severely limit the linearity and...
Precision operational amplifiers (opamp) with 30V supply operation have been widely used to support industrial, instrumentation, and other applications [1]. Most of them have been realized with BJT or JFET processes [1] to offer voltage noise PSD better than 10nV/√Hz and offset voltage drift better than 1μV/°C. Recently, opamps with similar specifications have become available using CMOS based processes...
As the demand for high-frequency DDR SDRAM increases, duty-cycle correction circuits (DCC) become a key element to widen the data-valid window (tDV). For duty detection in a DCC, analog schemes using charge pumps [1] and digital schemes using DLL locking [2] or time-to-digital converters (TDC) [3] are widely used. However, they require a certain amount of time proportional to duty errors or a high-resolution...
A multi-stage noise-shaping (MASH) architecture is an attractive approach for its aggressive noise-shaping capability and relaxed stability requirements. However, in practice the quantization noise leakage associated with the mismatch between analog and digital transfer functions degrades performance significantly. The discrete-time (DT) Sturdy-MASH (SMASH) architecture avoids this problem, and promises...
The fast adaptation of WiFi 802.11ac 256-QAM mode requires RF clocks with very low integrated phase error to deliver good EVM performance. On the other hand, smaller area and lower power are always desired for lower cost and longer battery life. This work presents a 28nm CMOS LO design for dual-band 802.11abgn/ac radio with overall architecture shown in Fig. 9.4.1. It addresses the aforementioned...
Signal acquisition systems for emerging applications, such as impiantatile or unobtrusively wearable autonomous sensors, large sensor arrays, or wireless self-powered sensors, require a minuscule form factor and very low power consumption. For example, the power available from a state-of-the-art 1mm3 solid-state thin-film battery is limited to 4nWfora 10yr lifetime [1], and a 1mm3 energy harvester...
In present digital circuits, low power consumption with high packaging density is always needed. The continuous reduction of MOSFET devices channel length causes an undesirable Short Channel Effects on the device parameters rendering large power dissipation. Increased leakage current with technology improvement requires tight control. In delay flip flop the storing of data get restricted due to leakage...
New low power dynamic MTCMOS full-adder cells have been proposed in this paper. Eight bit Domino and TSPC (True Single phase clock) adder circuits have been designed in 45 nm Multi-threshold CMOS Technology. The proposed MTCMOS dynamic adder circuits are faster as compared to static CMOS logic circuits. Due to the high-VT sleep transistor added, the leakage power of the circuits is also minimized...
While all computation generates electromagnetic (EM) side-channel signals, some of the strongest and farthest-propagating signals are created when an existing strong periodic signal (e.g. a clock signal) becomes stronger or weaker (amplitude-modulated) depending on processor or memory activity. However, modern systems create emanations at thousands of different frequencies, so it is a difficult, error-prone,...
In this paper, joint sensor synchronization and localization using time-of-arrival measurements is studied. In wireless sensor networks, the accuracy of the clock synchronization among nodes has a great impact on the performance of the localization using time-based ranging methods. The clocks of the anchor nodes are typically synchronized with each other, while those of the source nodes must be synchronized...
Capacitive sensing circuit for MEMS mirror based pico-projector scanning system is realized in this work. Two dimensional (2D) movements of the MEMS-mirror produce capacitive variations ΔCx and ΔCy. These are sensed and used to monitor and control the mirror movements in a closed feedback loop. The 2D mirror movement is produced using dual-actuation mechanism. High-voltage electro-static actuation...
This paper describes the architecture and schematic design of a 4 GS/s radix-1.75 pipeline ADC in 28 nm CMOS technology. Due to large mismatch effects, a foreground calibration procedure with characterization of the transfer functions of the single pipeline stages is necessary. The gained information is used in a pure digital backend calculation. This allows increasing the effective resolution to...
Increased functional density with shrinking technology could result in escalating noise-induced failures in the field. Further, the low correlation between system level functional test and production test is making it difficult to better screen parts that would fail in the field due to noise. To address these issues, in this paper we present a light-weight fully digital on-chip distributed sensor...
In this paper, we report our experiment about wavelet decomposition for study environmental condition based on infrared images. Infrared images acquired by consumer digital camera, after replacing the infrared stoping filter with filter SRS, and the images captured sequentially every two hours (from 06:00–16:00). The result of this research is the increasing air pollution characterized using wavelet...
In order to minimize the impact of on-chip Ldi/dt noise on power and performance, Oracle's SPARC M6 processor features an Asymmetric Frequency Locked Loop (AFLL) that dynamically adjusts chip frequency. It achieves 15% improved noise immunity by reacting to the voltage noise asymmetrically through the use of a pair of DCO's that accurately track the response of critical paths. The AFLL is implemented...
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