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A CMOS-based microelectrode array (MEA) with 4225 recording sites and 1024 stimulation sites and a related data acquisition system are presented. The chip provides high spatiotemporal resolution on an active area of 1 mm × 1 mm or 2 mm × 2 mm, respectively, and allows in-vitro neural tissue interfacing experiments with full imaging capability. The entire chip surface is covered by a thin high-k dielectric...
A wideband low noise amplifier is suitable for an emerging architecture such as a SDR and Digital RF. The gallium arsenide process has an advantage of very low noise figure at very high frequency. In this article we have taken efforts to propose a new concept for a wideband highly linear low noise amplifier. The simulations are carried out using Agilent Advanced Design System ADS to analyze the behavior...
Today, the diseases are being treated with less invasive and more sophisticated, technology-oriented methods. The diagnostic tools that were usually used in the hospitals have become available at our homes. Within the heart of this new generation health-care systems, CMOS technology lies with its high capability of integration, low power consumption, and low cost. Within this context, CMOS image sensors...
This paper presents a novel continuous time (CT) - discrete time (DT) current amplifier for electrophysiology. The architecture aims to bring together advantages from both CT and DT approaches, which are high bandwidth and low noise, respectively. The low-noise current amplifier has been implemented in 0.35 µm CMOS technology, showing input-referred noise as low as 4 fA/√Hz. It allows current recording...
III-V Tunnel FETs (TFET) possess unique characteristics such as steep slope switching, high gm/IDS, uni-directional conduction, and low voltage operating capability. These characteristics have the potential to result in energy savings in both digital and analog applications. In this paper, we provide an overview of the power efficient properties of III-V TFETs and designs at the device, circuit and...
A highly sensitive optoelectronic receiver circuit is formed by combining a 100 μm diameter avalanche photodiode with an integrated transimpedance amplifier (TIA). Both main components are fabricated in a 0.35 μm standard silicon technology. The highly efficient avalanche photodiode which bases on a modified pin structure with a large detection volume is operated at 30 V reverse bias to obtain avalanche...
This paper presents a two stage low noise chopper amplifier for integrated angular acceleration sensor signal processing circuit which consists of amplifiers, phase-locked loop and automatic gain control. Capacitor feedback amplifier circuit is one of the most suitable for CMOS technology however capacitor amplifier with chopped op-amp has poor low frequency performance because of parasitic resistive...
This paper shows a methodology to reduce electromagnetic radiation in typical CMOS digital systems from chip PDN design point of view. Total PDN property with anti-resonance peak can be strongly affected by on-die PDN property. Then, in order to suppress anti-resonance peak in total system PDN, design of chip PDN is more effective than off-chip damping method. Then, two similar test chips were designed...
This paper presents a novel CMOS active pixel sensor (APS) imager with fully digital global readout channel and continuous time on-chip energy harvesting. Imager captures low-noise images while consuming 140nW of power at 0.7 FPS. Imager has a 0.078% total FPN in dark. It generates 31μW power at bright daylight.
A wideband, fully differential, 3-stage class-AB amplifier capable of operation at rates beyond 100 Mbps is described. Common-mode feedback is applied to increase output drive capability and reduce bias-dependent crossover distortion when operating in class-AB from a low supply voltage. Drawing 3.9mA from a nominal VDD of 1.2V in 65nm CMOS, the 0.052mm2 amplifier delivers 1.6V swing across a 50Ω load...
This paper presents a tunable integrated electrical balanced duplexer as a compact alternative to multiple bulky SAW and BAW duplexers. A floating balancing network creates a replica of the TX signal for cancellation at the input of a single-ended LNA, thus enabling high power operation. It achieves around 50dB isolation within 1.6–2.2GHz range. The cascaded noise figure of the duplexer and LNA is...
Technology for producing practical and affordable 2D ultrasound arrays is crucial for expanding the clinical deployment of 3D/4D ultrasound imaging. In addition, low-cost planar arrays may enable revolutionary health monitoring devices that employ 3D data for real-time quantitative measurements of parameters such as such as blood volume flow or tissue motion. CMUT-in-CMOS technology allows high-volume...
A new method for the analysis of multilevel Random Telegraph Noise (RTN) signals has been recently presented, which can also be applied in the case of large background noise. In this work, the method is extended to evaluate the RTN-related variation of the device drain current. The RTN parameters obtained from experimental traces are used to simulate the impact of RTN in the drain current of pMOS...
This paper describes a tile-able 16-kByte 6-T SRAM macro in a High-K Metal-Gate (HKMG) 28-nm bulk technology with an operating window from 4.8 GHz at 1.12 V VDD down to 10 MHz at 0.5V, meeting almost all of the Dynamic Voltage Frequency Scaling (DVFS) requirements of Level-1 (L1) caches of a digital microprocessor SOC. It uses an unmodified technology-supported 0.156um2 high-current (HC) SRAM cell...
This paper presents a digitally calibrated 12bit 12.5-MS/s successive-approximation-register (SAR) analog-to-digital converter (ADC) intended for low-power wireless communication and medical instrumentation. The performance of the proposed prototype is enhanced by two techniques. A power saving strategy is proposed. Also, several foreground calibration methods for SAR ADCs are proposed to reduce the...
It is traditionally difficult to implement higher order PWM closed loop class-D audio amplifiers using analog techniques. This paper describes a mixed signal approach, implementing a 4th order amplifier in 55nm CMOS with minimal demands on a front-end ADC. An approach to design the feedback loop in the digital domain with high gain throughout the audio band (100dB at DC) to improve linearity and PSRR...
In this paper, a distributed amplifier (DA) with a feed forward path is presented to reduce noise effects of input matching termination at the output. The proposed active termination (AT) technique also improves the amplifier gain without increasing its power consumption. To validate the introduced method, a four-stage wideband actively terminated DA (ATDA) is designed in a 0.18μm CMOS technology...
This paper presents a novel dual slope charge sampling (DSCS) analog front-end (AFE) architecture, which amplifies neural signals by taking advantage of the charge sampling concept for analog signal conditioning, such as amplification and filtering. The presented DSCS-AFE achieves amplification, filtering, and sampling in a simultaneous fashion, while consuming very small amount of power. The output...
An approach towards a high speed current mode SAR ADC is presented. Even though SAR ADCs based on charge redistribution have been significantly improved in efficiency and operating frequency, they are still limited by the settling requirements of the switched capacitor DAC. To overcome this limitation, we propose the use of a current mode SAR ADC incorporating a current steering DAC operating at 2...
In this paper, a CMOS neural amplifier based on memcapacitor has been realized. A memcapacitor is a new element based on memristor. A performance comparison between memcapacitor based realization and conventional integrated one has been introduced. The circuits were simulated using 90nm CMOS technology, Vdd = 1.2v, for a total input referred noise of 1.97 µVrms and a total power consumption of 1.28...
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