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In this paper, a detailed analysis of the voltage transfer characteristics of vertical nanowire transistor-based CMOS inverter is presented. We show that noise margins are strongly dependent on the source/drain series resistance, and that the extension lengths can be used as tuning parameters to control the noise margin and gains of the inverter.
This paper presents a design of a low power single ended CMOS LNA for reconfigurable applications including GPS, GSM (DCS1800, PCS1900), 3G (UMTS), WLAN b/g and LTE. Based on a wideband input matching, the LNA stages cover all band of interest while achieving a good trade-off between high gain, low noise figure and low power consumption. For multi-standard aim, the LNA selects the desired bands using...
Low Noise Amplifier is the Front End Block of Radio-Frequency Receiver System. Various characteristics are Gain, Noise Figure, Insertion Losses and Power Dissipation is required in its designing. In this Paper we have surveyed almost all the Possible Work Done in Low Noise Amplifier in Past Decades. Here we will Study about Varying Range of Noise Figure, Gain, Power Consumption and Different Methodologies...
As technology scales into the nanometer regime ground bounce noise and noise immunity are becoming important metric of comparable importance to leakage current, active power, delay and area for the analysis and design of complex arithmetic logic circuits. In this paper, low leakage 1bit full adder cells are proposed for mobile applications with low ground bounce noise and a novel technique has been...
In this paper, a novel design technique of common-source inductive degenerated 60GHz low noise amplifier is presented for millimeter-wave range. For this technique, by adopting inductor at the common source transistor of the cascode stage, the gain of the LNA can be enhanced even under a narrow band operation of 57GHz to 63 GHz. Using a 90nm CMOS processcvvg, from a 1.2-V supply voltage, Low Noise...
This paper presents an experimental analysis of the impact of AC- and DC-type Negative Bias Temperature Instability (NBTI) stresses on the CMOS inverter DC response and robustness. The results reveal, on one side, that the inverter DC response under AC NBTI presents a parallel shift of that shown under DC NBTI. However, the AC- to DC-induced shift of the inverter logic threshold is found much less...
In this paper forward body bias technique is implemented on a low noise amplifier to improve its noise figure and gain. The forward body bias is applied in the conventional Low-Noise Amplifier design which accounts for the low Noise-Figure and high Gain in it. The cascode LNA operating at 24 GHz without forward body bias is compared with the LNA having forward body bias using the PTM 65-nm technology...
This paper describes the architecture and schematic design of a 4 GS/s radix-1.75 pipeline ADC in 28 nm CMOS technology. Due to large mismatch effects, a foreground calibration procedure with characterization of the transfer functions of the single pipeline stages is necessary. The gained information is used in a pure digital backend calculation. This allows increasing the effective resolution to...
This paper presents a new method for sizing the transistors in CMOS gates as an enabling technique for green technology. The technique utilizes an efficient feedback-based system to optimize the transistors sizes in the gates with the fanins of 2 or more. The optimized NAND2-4 gates provide nearly 65% savings in power dissipation and 58% reduction in energy consumption, as compared to their normal,...
Noises and variations are ubiquitous, but are still being ill-understood and in most cases treated simplistically, leading in most cases to substantial overdesign costs. A novel reliability-centric design method based on unconventionally sizing transistors has been suggested lately. In this paper our aim is to design, simulate, and compare the benefits of unconventional sizing when applied to ultra-low...
A 0.6V 10-bit 150MS/s single-channel asynchronous subranging SAR ADC using a settling-time relief technique is presented. The technique extends the allocated DAC settling time with the assistance of a coarse ADC and minimizes digital loop delay so that it can reach high speed and low power at a 0.6V supply. This ADC consumes 0.264mW at 150MS/s in 40nm CMOS technology. It achieves an SNDR of 50.5dB...
This paper describes the design of an indirect current feedback Instrumentation Amplifier (IA). Transistor sizing plays a major role in achieving the desired gain, the Common Mode Rejection Ratio (CMRR) and the bandwidth of the Instrumentation Amplifier. A gm/ID based design methodology is employed to design the functional blocks of the IA. It links the design variables of each functional block to...
A new reconfigurable linearized low noise transconductance amplifier (LNTA) design for a software-defined radio receiver is presented. The transconductor design aims at realizing high linearity at RF in a way that is robust for Process, Voltage and Temperature variations. It exploits resistive degeneration in combination with a floating battery by-pass circuit and replica biasing to improve IIP3 in...
This paper presents a novel topology of low-noise amplifier (LNA) with noise reduction and gain improvement. A transformer feedback gm-boosting technique is proposed in a single-ended cascode LNA to reduce the noise figure (NF) and improve the gain simultaneously. Two 54 GHz single-ended cascode LNAs, with transformer and transmission-line for matching, respectively, are demonstrated to verify this...
Future computing systems spanning exascale supercomputers to wearable devices demand orders of magnitude improvements in energy efficiency while providing desired performance. The system-on-chip (SoC) designs need to span a wide range of performance and power across diverse platforms and workloads. The designs must achieve robust near-threshold-voltage (NTV) operation in nanoscale CMOS process while...
In this paper, a highly linear, inductively degenerated, common source narrowband LNA is presented. An extremely simple feed-forward distortion circuit (FDC) which consists of an appropriately sized ac-coupled diode connected NMOS is proposed. This circuit generates distortion components at output, when added at the input node as a feed forward element (M6). These distortion components partially cancel...
Here, we report on design and measurement results of a state of the art low-noise and high-gain transimpedance amplifier (TIA) implemented in 0.18 μm TSMC CMOS technology. In depth design methodology for design of high gain and low noise TIA for 2.5 Gb/s optical communication family is presented. A novel noiseless capacitive feedback is proposed and implemented as a noise efficient feedback for TIA...
A wideband resistive feedback balun low noise amplifier (LNA) is presented in this paper. The proposed LNA has a wide band gain of 22 dB in a band of 0.2–5 GHz. An improved input balun stage is used to realize a single-ended to differential conversion with optimized transconductance and amplifier open-loop gain. The wide band LNA is implemented in 65nm CMOS technology and has an area of about 0.009...
This paper presents the design of a CMOS low noise amplifier (LNA) with minimized group delay variations and optimized noise performance for ultra-wideband (UWB) applications. The proposed LNA employs a common source based current reuse topology. Through this configuration gain flatness of 12.25± 0.25 with noise figure (NF) less than 3.8 dB are achieved. This LNA achieves group delay variation of...
This paper presents the design of a CMOS low noise amplifier (LNA) with minimized group delay variations and optimized noise performance for ultra-wideband (UWB) applications. The proposed LNA employs a common source based current reuse topology. Through this configuration gain flatness of 12.25± 0.25 with noise figure (NF) less than 3.8 dB are achieved. This LNA achieves group delay variation of...
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