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This paper presents an improved design of active RF CMOS double balanced Gilbert mixer. The designed mixer adheres to the IEEE 802.15.6 standard and can be used for WBAN applications, particularly for biomedical applications. The Designed circuit has been optimized for high conversion gain, high linearity and low power consumption. RF frequency used is 2.4GHz that is ISM band. LO frequency is 2GHz...
In this paper, A complementary metal oxide semiconductor low noise amplifier (CMOS-LNA) is designed for ultra low noise and low power applications in 90nm CMOS technology at 2.4 GHz IEEE 802.15.4 standard. In order to meet the requirement of the ultra low voltage and low noise applications, a differential stage capacitive cross coupled common gate configuration is employed. The proposed capacitor...
In this paper, an ultra low power CMOS common gate LNA (CGLNA) with a capacitive cross-coupled (CCC) gm boosting scheme is designed and analysed. The technique described has been employed in literature to reduce the noise figure (NF). In this work we have extended the concept for low voltage operation along with improving NF and also for significant reduction in current consumption. A gm boosted CCCCGLNA...
In this paper, a novel design technique of common-source inductive degenerated 60GHz low noise amplifier is presented for millimeter-wave range. For this technique, by adopting inductor at the common source transistor of the cascode stage, the gain of the LNA can be enhanced even under a narrow band operation of 57GHz to 63 GHz. Using a 90nm CMOS processcvvg, from a 1.2-V supply voltage, Low Noise...
In this paper we preset implementation of an optimized Sobel edge detection algorithm on FPGA. The optimized gradient based edge detection method reduces the area up to 48.76% compared to existing gradient calculation unit, and also reduces propagation delay up to 51% compared to the area optimized architecture. The entire project is implemented on Spatran-3E FPGA board. VGA interface is used to display...
This paper is about the design of an SPI interface which is based on the specifications mentioned in the SPI block guide V03.06 by Motorola. The present design includes an additional power down mode-stop mode for power optimization and the standard design has been modified by the technique of clock gating for additional power reduction. The shifter module of the interface has been designed with double...
The paper discusses the design of an SPI interface based on the specifications mentioned in the SPI block guide V03.06 by Motorola. The present design incorporates additional power down mode - stop mode for power optimization and the standard design was modified by using clock gating technique for additional power reduction. The shift registers are replaced by double buffer registers to prevent the...
In this paper we present the VLSI implementation of STM-1 Framer and De-Framer. This paper mainly focuses on multiplexing digital data, transmitting and receiving the STM-1 frame. The design is implemented using Verilog HDL, simulated on Modelsim and Synthesized on Xilinx ISE 13.2. For power analysis and area calculation, the designed framer and de-framer are analyzed using Cadence version 6.1.5....
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