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An SoC with ARM® Cortex™-M0 CPU cores and SRAMs is implemented in both 65nm baseline and Deeply Depleted Channel™ (DDC) technologies. DDC technology demonstrates more than 50% active and static power reduction for the CPU cores at matched 350 MHz speed via VDD scaling and body biasing. Alternatively DDC technology demonstrates 35% speed increase at matched power. The results hold across process corners...
For the operation of a successive approximation register analog-to-digital converter, an integrated reference voltage source is required. This reference has to be stable and has to have high precision. Therefore, trim mechanisms for the achievement of optimal accuracy and minimum temperature drift behavior are necessary.
In this paper, a pixel for time-resolved single photon detection is presented. The pixel includes a passively quenched Single-Photon Avalanche Diode (SPAD), a gating circuit and an analog counter based on charge sharing approach. The analog output signal delivered by the pixel is quantized in discrete levels, corresponding to different photon counts. Three linear arrays with different pixel versions...
Based on the Gilbert Mixer topology, an active mixer operating at 2.15 GHz is designed by using the transistors which are realized by using 0.25um SiGe technology. The active balun circuit at the input is realized by using the CB(common base) and CE(common emitter) transistors. The passive capacitive voltage-series feed-forward circuit is applied to CB circuit and an almost perfect broadband matching...
We present a modified type-I level-up shifter with improved Process-Voltage-Temperature (PVT) robustness, propagation delay and energy consumption. Compared to a standard cross-coupled level-shifter, the circuit comprises a couple of long channel parallel P and N transistors to implement larger PMOS on-resistance maintaining unvaried upstream logic fan-out. Simulation results show significant robustness...
Passive cancellation of common mode (cm) noise is a very promising alternative to a conventional cm filter. The basic idea has already been described in literature. However, a thorough theoretical investigation regarding the flyback that shows that perfect compensation should be possible, has not been published yet. The investigation given provides a deeper insight into passive compensation and balancing...
Multi-Threshold CMOS (MTCMOS) is one of the most used circuit techniques to reduce the leakage current in idle circuit. Ground bounce noise produced during transition mode (Sleep-to-Active) is an important challenge in MTCMOS. In this paper we have designed our multiplier with different MTCMOS techniques to reduce the ground bounce noise and leakage current. The dependence of ground bounce noise on...
This paper describes design techniques for Bipolar and BiCMOS analog circuits. Comparison on such performances as transconductance, speed, matching, noise of bipolar and CMOS transistors are reviewed and compared. Design achievements such as a single core 12 Bit 1.5GS/s Analog to Digital Converter (ADC) [1] and a single core 12 Bit 3GS/s Digital to Analog Converters (DAC) [2] based on a fully bipolar...
This paper proposes new circuit architecture readout for X-ray pixel detector for imaging based on the design of the integrating and single photon processing pixel array. The proposed architecture design provides a balance between single photon processing mode and the integrating mode. This leads to a good compromise of circuit complexity. We show that the increase of complexity, will lead to increase...
The conventional power delivery analysis applying Icc(t) approach has the propensity to yield pessimistic outcome that leads to power delivery network (PDN) over-design. In addition, the noise profile captured using Icc(t) approach has high prospect of miscorrelation with the lab measurement data. Recent works adopting the signal integrity and power delivery (SIPD) co-simulation approach was found...
Semiconductor nanowires are typically fabricated into transistors using metal source and drain contacts but no doping profile, leading to devices that operate as Schottky-barrier field effect transistors rather than traditional MOSFETs. Because of this fundamental difference in geometry, the devices will operate with greater influence from the contacts in both current and noise behavior, yet many...
In this paper a 1.8 V, 2.4 GHz CMOS fully integrated low noise amplifier (LNA) has been implemented in 0.18 µm RF CMOS process for Wireless Local Area Net (WLAN) and Bluetooth band. Acceptable consumption with higher voltage and power gain are achieved using traditional cascode configuration. In this configuration, we successed to have a good trade off among noise, gain, and stability. In order to...
We report on terahertz wireless communication experiments at 0.2 THz, using a commercial GaAs field-effect-transistor as detector. For the first time, we will present the transmission of pseudo-random bit sequence at 0.2 THz using this commercial transistor and demonstrate open eye-patterns up to 1.5 Gbps. This transistor is integrated into a machined horn, so that its sensitivity is improved to 1...
The effectiveness of activation noise aware ultra low power diode based multi-threshold CMOS circuit technique to deal with activation noise and standby leakage current is evaluated in this paper. An additional wait mode is introduced to gradually dump the charge stored on the virtual ground line to the real ground line during the sleep to active mode transition. Ultra low power diode based MTCMOS...
This paper deals with the design of a low power signal conditioning circuit for use in biomedical applications. The signal conditioning circuit constitutes an opamp serving as a preamplifier and a low-pass filter for rejecting higher frequency components which are uncharacteristic of bio-medical applications. The Operational Transconductance Amplifier (OTA) design is done using UMC 180nm CMOS technology...
Recent studies have shown that transistor variability and ageing phenomena are responsible for variation of transconductance (gm) and drain current (ID) in MOSFETs. It is therefore important to perform sensitivity analysis at the earliest design stage in order to minimize effects of ageing. It is however not trivial to perform sensitivity analysis analytically because the 1-V characteristics of modern...
The main objective of this paper is to give an overview of different hybrid MRAM/CMOS cells to use in the context of reconfigurable computing. The way to convert magnetic information into an electrical one is not unique and we propose to compare different kind of hybrid cells. These hybrid cells can be used to define structures as Look-up Table, configuration memory point, Flip-flop and other basic...
We study scaling behaviour of terahertz responsivity and low-frequency noise of silicon MOSFET-based detectors. A set of 550-GHz resonant patch-antenna-coupled transistors with different channel widths varying from 320 nm to 1920 nm have been fabricated and investigated in temperature range from 77 K to 360 K. We find that the best sensitivities are achieved for narrowest devices without applied bias...
A design methodology of reconfigurable distributed low noise amplifier (RDLNA) dedicated for wireless home communications operating from 0.8GHz to 11GHz is presented in this paper. This RDLNA is suitable to operate in two different operation modes: low power consumption mode and high performance mode. The used technology is 0.15μm InGaAs Active Layer pHEMT Process provided by TRIQUINT. The circuit...
A two-stage charge sensitive amplifier architecture suitable for semiconductor radiation detector with large capacitance is proposed. The integration capacitor of the first stage can be made large to reduce gain sensibility to detector capacitance without any stability problem. Each stage uses a self-biased MOS transistor to discharge the integration capacitor. The self-bias circuit tracks process,...
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