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A novel sequential inter-stage correlated double sampling technique has been proposed. This technique provides considerable enhancement in the effective accuracy of a switched-capacitor architecture. Superior accuracy and thermal noise performance is achieved compared to the conventional correlated double sampling technique. The proposed approach provides higher input signal bandwidth by reducing...
An area-efficient and low-power low-noise amplifier with adjustable parameters for bio-potential recording applications is presented. This amplifier replaces traditional analog filters using large AC coupling capacitor with the proposed DC offset suppression block based on Differential Difference Amplifier (DDA) structure, which allows the system to obtain good high pass characterization without using...
In this paper, a slot type high impedance surface and a mushroom type high impedance surface are applied respectively for the noise reduction inside the shielded package. A simple and efficient modelling method is proposed for the high impedance surface design. A commercial chip with its package is employed to show the performance of the proposed high impedance surface. Both simulation and measurement...
This paper studies the methodology of power integrity (PI) analysis for high speed printed circuit board (PCB) design. This involves the analysis of AC and DC characteristic of the PCB, and also the loop stability of the switch mode voltage source. Besides this, the best practices of designing a power rail with excellent fidelity are discussed in detail in this paper. The basic theory of operation...
This paper presents the design and simulation of High gain Source degenerated Cascode LNA for Wi-max and W-CDMA applications at 3.5GHz. The design uses an enhanced cascade topology to attain improved forward gain and noise figure. Th is design includes lumped elements like inductor, capacitor and resistors to design input and output matching networks. The targeted narrow-band gain, impedance matching...
Smartphones deploy multiple microphones to reduce background noise, reverberation and interferences. This paper presents the regulated Frost beamformer (REF) for acoustic gain enhancement and speech recognition improvement in smartphones. Conventional and adaptive beamformers were investigated with recourse to the acoustic transducer specifications of the Samsung Galaxy S2 device. The REF algorithm...
Cellular network operators are constantly seeking ways to improve network capacity and coverage performances without resorting to use of additional costly frequency spectrum. One of the most effective methods is to reduce the azimuth beamwidth of the antennas by using multiple directional antennas in the azimuth direction, or higher order sectorization [1][2]. This method has recently been proven...
A two-stage MMIC low noise amplifier design is presented using series and shunt feedbacks to achieve simultaneously low noise, input matching and gain flatness performances across the frequency range of 4 to 12 GHz. The amplifier fits into a small die of 2×1 mm2, and achieves a flat gain of 20 dB and a minimum noise figure of 1.5 dB.
Devices fabricated through TSMC 0.18 micron CMOS process are modeled and implemented in Agilent ADS for the circuit designs. Two low-noise, well impedance-matched radio frequency amplifiers working at various nearby center working frequencies, 2.6 GHz and 2.8 GHz, are proposed using Class-E power amplifier mechanism. Both are deliberately put in series such that both can couple with each other, The...
Hybrid microwave integrated circuit technology is used to design and develop an L-band (900–2100 MHz) ultra-low noise amplifier for the MeerKAT array. This low noise amplifier achieved 2 K noise temperature, more than 40 dB gain, S11 & S22 better than −11 & −15 dB at 15 K ambient. Linearity and gain compression is verified. The noise performance is explored as the cooling temperature changes...
We present a 1-GΩ CMOS transimpedance amplifier (TIA) suitable for processing sub-nA-level currents in electrochemical biosensor signal-acquisition circuits. Use of a two-stage active transconductor provides resistive feedback in place of a single large-area linear resistor. We engineer the TIA feedback loop to suppress output offset caused by dc input leakage currents of ±0.9 nA. We also implement...
Mammography is the most used diagnosis method for the breast cancer. The challenge of this exam is to obtain good contrast and resolution with small radiation doses. In recent years, several efforts have been done to improve the detection efficiency of mammograms by using the potential offered by digital image processing. In this work, the potential benefits of applying the wavelet transform for microcalcifications...
The design, packaging, and characterization of a 70–95 GHz downconverter with 25 GHz of instantaneous bandwidth is presented. The circuit features a novel LO pass-through feature, making it suitable for integration in two-dimensional focal plane arrays with large-N. The chip has been packaged in a waveguide module and, in the packaged configuration, has a noise temperature below 2000 K (9 dB NF) and...
Bypass low-noise amplifier (LNA) can be used in the base station receiver to improve the dynamic range. It is difficult to achieve both ultra low noise at LNA mode and maintain good linearity at bypass mode simultaneously. In this work, we present the best performance bypass LNA with 0.5 dB of noise figure (NF), 20 dB of gain at 1.95 GHz and high OIP3 of 35 dBm for both LNA and bypass mode. Fabricated...
This paper presents a new technique for the design of receiver architectures, based on the use of variable reference voltages in ADCs. The main goal is to improve the SNDR of a receiver chain when compared to traditional architectures like Low-IF or Subsampling, while performing down-conversion without the need of a Mixer block. The proposed technique takes advantage of the inherent capability of...
403-MHz fully differential RF LNA was designed and implemented using 0.13 µm CMOS process. This design was targeted for low-power and low-cost direct conversion applications such as short-range radio in biomedical devices. This design consists of a differential CG-CS LNA with a positive- negative-feedback technique. The LNA occupies 150 µm× 120 µm active chip area, which is approximately 50% of that...
We present a 200 MS/s 2x interleaved 14 bit pipelined SAR ADC in 28nm digital CMOS. The ADC uses a new residue amplifier for low noise at low power, and incorporates interleaved channel time-constant calibration. The ADC achieves a peak SNDR of 70.7 dB at 200 MS/s while consuming 2.3 mW from an 0.9 V supply.
Proposed is a two-stage amplifier exploiting recycling current-buffer Miller compensation (CBMC). By reusing the most current-consuming devices in the 1st stage as current buffer, such an amplifier not only can preserve the merits of typical CBMC implementation in creating the beneficial left-half-plane (LHP) zero, but also can avoid the drawbacks of typical CBMC scheme from degrading the power efficiency,...
A 100 Gb/s CMOS transimpedance amplifier (TIA) for high speed optical communication receivers is presented in this paper. The TIA is based on a differential architecture and composed of a regulated cascode block and a differential amplifier with active feedback. It adopts peaking inductors and a capacitive degeneration scheme to increase the bandwidth. The TIA is designed and laid out in CMOS 65 nm...
A discrete-time, switched-capacitor, MASH 2–2 4th order ΣΔ modulator, clocked with frequency of 1 GHz, was designed in a 65 nm CMOS technology. This modulator uses passive integrators based on the ultra-incomplete settling (UIS) concept. Electrical simulations show that the modulator achieves a peak SNDR of 66.8 dB, a peak SNR of 67.7 dB, an ENOB of 10.8 bits and DR of 70dB for a signal with a bandwidth...
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