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Impact of donor-layer doping concentration and temperature variation on the various noise coefficients and minimum noise figure is investigated for separate gate InAlAs/InGaAs DG-HEMT, in this paper. The noise coefficients, which include the drain noise coefficient (P), gate noise coefficient (R), the correlation coefficient (C) and the minimum noise figure have been evaluated using Pucel's charge...
Domino dynamic circuits are widely used in critical parts of high performance systems. In this paper we show that in addition to the functional limitation associated to the non-inverting behavior of domino gates, there are also performance disadvantages when compared to inverting dynamic gates, which can be related to this feature. These penalties rise from the fact that in order to produce a logic...
In this work, the risk-sensitive optimal control equations for polynomial stochastic systems of third degree with exponential criterion to be minimized and parameter of diffusion into the state equations has been applied to the Fitz Hugh-Nagumo (Bon Hoeffervan der Pol) model. This model represents an excitable system with driven noise, which could be associated with diverse processes, from the kinetic...
In the course of years, several models have been put forward to explain noise phenomena, bias temperature instability (BTI), and gate leakage currents amongst other reliability issues. Mostly, these models have been developed independently and without considering that they may be caused by the same physical phenomenon. However, new experimental techniques have emerged, which are capable of studying...
We present a theoretical study on the temporal current fluctuation in nanowire FET caused by the presence of a single gate oxide trap through the Coulomb interaction. Our calculations based on the scattering theoretical formulation of the current noise showed that the presence of the trap level in the gate insulator gives rise to the enhancement of the noise at a specific gate voltage. The peak position...
DC Motors are quite common in large number of applications ranging from small tools to large industrial machines. Efficiency of such machines depends on proper operation of these motors to a much larger extent. Moreover, heavy duty applications require high current demanding motors. High current also leads to addition of other noise issues. Here we put forward a high performance motor drive circuit...
Currently, driving power circuits at high switching frequency is performed in order to downsize and lighten switching power supplies. Along with it, wide band gap semiconductor devices, GaN and SiC, have attracted attention. However, there is a great constrain related to the false turn-on phenomenon produced by gate noise because these wide band gap semiconductor devices have low threshold voltage...
In this paper, a power reduction technique for wideband common gate low noise amplifiers (LNA) is proposed for low power application. Stacked current reused complementary capacitive cross coupling (CCCC) concept is proposed to improve LNA power efficiency. As a proof of the concept, the improved broadband differential common-gate LNAs (CG-LNA) designed in 0.18µm CMOS technology. The LNA achieves a...
The estimation of dependable noise margins in digital cells is increasingly significant as nano-scale CMOS technology is facing true reliability issues. On one hand, a major concern comes from circuit aging mechanisms, such as NBTI, which degrade the reliability of circuit operation over time. On the other hand, variability in technology parameters results in affecting reliability. The impact of such...
Variations and noises are ubiquitous, but are still poorly understood and analyzed simplistically, leading in most cases to substantial overdesign. Lately, a novel reliability-centric design method based on unconventionally sizing transistors has been suggested. In this paper our goal is to design, simulate, analyze and compare the benefits of unconventional sizing when applied to ultra-low voltage/power/energy...
The paths for power supply noise leakage in low drop-out (LDO) voltage regulators are analyzed, and techniques are discussed to minimize their effects on the output voltage. An internally compensated high power supply rejection (PSR) LDO voltage regulator with adaptive supply noise compensation scheme is presented. Its regulated output voltage is 1.6 V to provide 0–50 mA of current with a power supply...
In this paper, a novel analytical model is proposed to predict the delay variation due to the power supply noise in nanotechnologies. First, an analytical model is derived for the special case of an inverter gate; next, it is shown that the derived model can also be applied to the other gates. The proposed analytical model helps us to better understand the main contributors to the delay variation...
Noise caused by switching voltage regulator (VR noise) can have a big impact on system signal / power performance, leading to signal integrity (SI) / power integrity (PI) issues. This paper introduces systematic ways of reducing VR noise as well as VR noise analysis methods. And a real design case with VR noise issue is shared with simulation and measurement results.
We propose a method to suppress the electrolyte potential noise in time-dependent protein sensing tests with an additional reference electrode, which doesn't have the challenging requirements as for the reference FET (REFET). The noise is recorded by the additional electrode and then suppressed in the sensing results. This noise is likely due to the electrochemical reaction at the electrolyte - solution...
Motivated by the growing desire for low power design as well as the stochastic behavior of electronic circuits, the probabilistic computing based on inherently stochastic devices has been proposed. The single-electron (SE) technology is a promising candidate for implementing probabilistic switches due to its intrinsic mechanism and nanoscale feature size. In this paper, we analyze the stochastic behavior...
Ongoing technology scaling has increased delay defects in integrated circuits. Some of the delay defects are due to crosstalk, supply noise, process variations, etc. They degrade the performance and field reliability of circuits. However, testing the circuits with path delay patterns under worst-case conditions helps to detect such defects. Estimation of patterns with worst-case path delay becomes...
In this paper we present FF-DICE (Footless-FinFET-DICE), an 8T footless storage element that exhibits soft error resilience characteristics to Single Event Upsets. The proposed cell utilises IDG (Independent Dual Gate) FinFETs to merge the functions of a typical cell's NMOS drivers and NMOS access transistors, thereby saving 33% of the transistors required for a typical DICE cell. Given the IDG FinFET...
The time-periodic property of the LCD VCOM noise is utilized to reduce the effect of the VCOM noise on the mutual-capacitance measuring touch sensor placed on a LCD panel. The amplitude of the touch sensor driving signal (VSTM) can be reduced reliably down to 0.4 V with the reporting rate of 189 Hz, by using the following two methods. (1) The frequency of VSTM is set to (n+0.5)·fN, by synchronizing...
A very simple power supply rejection ratio (PSRR) enhancement technique is presented. It is suitable, among others, for low voltage power low power (LVLP) DC circuits such as biasing circuits. It is shown that a high insensitivity to AC noise in supply rails can be achieved with an almost zero contribution to the total internal noise. This is achieved at the expense of very small additional circuitry...
A novel digital calibration technique is proposed to calibrate the capacitor mismatch in SAR ADCs. The capacitor mismatches are extracted based on the comparator metastability and intrinsic noise. The proposed technique does not require additional external control sequences or any modification of the main DAC. The simulation results of a 12-bit SAR ADC with 10% capacitor mismatch show that the SNDR...
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