The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Among power dissipation components, the leakage power has become more dominant with each successive technology node. A power gating technique has been widely used to reduce the standby leakage energy. In this work, we investigate the power gating strategy of TSV-based 3D IC stacking structures. Power gating control is becoming more complicated as more dies are stacked. We combine the on-chip PDN and...
Current CMOS technologies show an increasing susceptibility to a rising amount of failure sources. This includes also radiation induced soft errors, which requires countermeasures on several design levels. Hereby, Bulk Built-In Current Sensors represent a promising approach on circuit level. However, it is expected that these circuits, like similar sensors measuring substrate effects, are strongly...
In this paper, a proposal to calculate the impedance frequency response of a power distribution network (PDN) is presented. Using the proposed algorithm, power planes have been modeled as an array of regular rectangles or squares constructing blocks like lego type which have been defined in terms of analytical equations given by the pi model. Transition via models has been obtained by using an approach...
In this paper, channel noise scan approach (CNS) is proposed to efficiently analyze the potential VR-signal coupling issue in the pre-silicon design and the post-silicon debug of the platform development. CNS is based on a new simulation methodology that includes the whole PCB with signals, voltage regulator (VR) networks, and the interaction between the two. The goal of this simulation methodology...
Aims: This theoretical investigation aimed to increase the dynamic range of a pulse oximeter by reducing electronic noise in the photoplethysmogram (PPG) using characteristics of the heart rate (HR) signal. The PPG is used to measure blood oxygen saturation (SpO2).
The flyback switched mode power supply often fails in electromagnetic compatibility (EMC) because of the easily aroused conducted electromagnetic interference (EMI). However, the measurement of conducted EMI during initial compliance tests requires strict test environments and expensive facilities, this makes the prediction of EMI important. This paper presents a time domain simulation method to predict...
This paper introduces a practical methodology to improve power integrity performance of the chip-package-PCB systems for smart TVs. For power integrity analysis, a chip, package and PCB are modeled as lumped element circuits for simplicity. Case studies are presented to optimize MLCC placement using chip-package-PCB co-simulation under fixed SoC design. In case studies, CPU power net of an application...
The output voltages at parallel simultaneous switching output (SSO) channels are affected by impedance of power distribution network (PDN) and SSO patterns. In this paper, a target impedance for PDN is directly extracted from the allowable signal output variations due to the SSO patterns.
In this paper, A novel wide-band uniplanar electromagnetic band gap (EBG) structure composed of complimentary split ring resonator (CSRR) and X shape bridge, called the X-CSRR EBG structure, is proposed to suppress ground bounce noise (GBN) and simultaneous switching noise (SSN) in power ground plane. Compared with conventional uniplanar EBG structures, such as the AI-EBG structure and the S-EBG structure,...
Proper transmission of high speed signal requires sufficiently high bandwidth of the medium. The reference planes play a vital role in achieving distortion-free signal propagation. In this paper a BGA package design exhibiting resonance conditions in insertion loss is analyzed. Analysis led to ground path issues caused by return current density congestions. Improvement in ground return path layout...
Three dimensional ICs are expected to bring about a new generation of integration by allowing for a smaller footprint, faster operation, and lower energy consumption. Manufacturing defects in through-silicon via (TSV) and disconnection defects among tiers are concerns in this new technology. To prevent yield loss from these defects, confirming known-good-die (KGD) and known-good-stacks (KGS) by test...
As technology scales into the nanometer regime ground bounce noise and noise immunity are becoming important metric of comparable importance to leakage current, active power, delay and area for the analysis and design of complex arithmetic logic circuits. In this paper, low leakage 1bit full adder cells are proposed for mobile applications with low ground bounce noise and a novel technique has been...
This paper presents an analog front-end (AFE) IC for measuring biopotential signals such as electroencephalogram (EEG) and, electrocardiogram (ECG). The AFE employs the capacitively coupled chopper instrumentation amplifier architecture to achieve low noise. To reduce chopper ripple and respiration artifacts, a continuous-time AC-coupled ripple reduction loop (RRL) and DC servo loop (DSL) are employed...
A thorough approach to the location and origin of traps generated in InGaP/GaAs heterojunction bipolar transistors (HBT) by low frequency noise characterization and reliable physics-based simulation is discussed. Physics-based simulation together with the low frequency equivalent short-circuit current noise sources (Sib, Sic) experimental results reveal an electron trap located at the 5-InGaP/GaAs...
This paper presents a new method for sizing the transistors in CMOS gates as an enabling technique for green technology. The technique utilizes an efficient feedback-based system to optimize the transistors sizes in the gates with the fanins of 2 or more. The optimized NAND2-4 gates provide nearly 65% savings in power dissipation and 58% reduction in energy consumption, as compared to their normal,...
A new neural approach for extraction of the Pospieszalski's noise model parameters of microwave FETs is presented in this paper. This approach is based on the use of two artificial neural networks. The first network is aimed at calculating the intrinsic noise parameters from the given equivalent circuit parameters, transistor total noise parameters, frequency and ambient temperature. Since the gate...
Modeling and analysis of low frequency noise in circuit simulators with time-varying bias conditions is a long-standing open problem. In this paper, we offer a definite solution for this problem and present a model for low-frequency noise that captures the internal, stochastic dynamics of the individual noise sources via dedicated internal pseudo nodes that are coupled with the rest of the circuit...
The conducted EMI simulation plays an important part in the SMPS in the product design. The analysis of common mode noise is much more complex than differential mode noise. The CE simulation accuracy depends on the accuracy of CM mode noise. CM noises are determined by the electric coupling between the voltage jump point and the ground. Traditional the CM models of the electric coupling between the...
Power supply noise is a serious issue for advanced CMOS LSIs and systems, since the performance of LSI chip is becoming more sensitive to power supply fluctuation under the lower power supply voltage. Because power supply noises are strongly related to the anti-resonance peak frequency in the total power distribution network (PDN), suppressing the anti-resonance peak is one of the most important design...
A scalable HEMT noise model has been developed, based on a lumped parasitic network extracted analytically through full-wave electromagnetic simulations and a scalable black-box representation of the intrinsic noise and AC response of the device. The analytical extraction of the lumped parasitic network is extensively explained, as well as the intrinsic model identification. The model prediction capability,...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.