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A 0.6V 10-bit 150MS/s single-channel asynchronous subranging SAR ADC using a settling-time relief technique is presented. The technique extends the allocated DAC settling time with the assistance of a coarse ADC and minimizes digital loop delay so that it can reach high speed and low power at a 0.6V supply. This ADC consumes 0.264mW at 150MS/s in 40nm CMOS technology. It achieves an SNDR of 50.5dB...
In this paper, we demonstrate our STO thin film decoupling capacitor embedded in organic interposer is effective for reduction of resonant power supply noise of LSI. By comparison of Shmoo plots with on-chip MOS capacitor, significant contributions of STO capacitor to higher operable frequency and lower power supply voltage are shown.
The electromagnetic interference (EMI) filter plays an important role in the EMI noise suppression. As the development of the switch mode power supply (SMPS), the power density of the SMPS improves every year. As a result the distance between components becomes smaller and smaller. The near-field magnetic coupling between components becomes larger and larger. However there are fewer studies about...
In the design of high complexity systems, the significance of signal integrity plays a vital role and in turn depends on the occurrence of different noises such as crosstalk noise, reflection noise, switching noises and active periodic noise. These noises are more in the design of IC, PCB layout design and multilayered PCB. However the impact of Simultaneous Switching Noise (SSN) noises in a IC with...
Since the loss of input rectifying diode bridge in the conventional PFC converter reduces the efficiency, the bridgeless PFC converter has been proposed. The totem-pole bridgeless PFC converter is the most representative one. However the common mode noise current occurring around the input voltage zero-crossing brings severe EMI problem restricts its practical application. In order to improve noise...
Power supply noise is a serious issue for advanced CMOS LSIs and systems, since the performance of LSI chip is becoming more sensitive to power supply fluctuation under the lower power supply voltage. Because power supply noises are strongly related to the anti-resonance peak frequency in the total power distribution network (PDN), suppressing the anti-resonance peak is one of the most important design...
A chopped capacitively-coupled instrumentation amplifier (CCIA) with a proposed duty-cycled Gm-C DC servo loop (DSL) for bio-potential signal acquisition is presented. The proposed architecture realizes a large time constant with small circuit area without sacrificing noise and power performance. Furthermore, this pseudo-resistor-less design grants this architecture easily portable for more advanced...
We present a 56-channel neural recording interface with a chopper-stabilized DC-coupled front-end and a programmable mixed-signal DC cancelation feedback. Each recording channel has a fully-differential amplifier with 51–54dB of gain, an input-referred noise of 5µVrms integrated from 10Hz to 5kHz and a CMRR of 65dB. Input DC-coupling allows for a simple chopping scheme without the area overhead of...
Power loss at the output stage of conventional constant current neural stimulators is notably high. This is particularly disadvantageous for applications in implantable systems where power budget is limited. We present a novel electrical stimulator architecture for significantly reduced power loss and low noise operation. The system generates a calibrated output voltage profile for driving electrode...
A novel method of using complementary split-ring resonators (CSRRs) structure in power/ground plane pair for wideband simultaneous switching noise (SSN) isolation is presented. Compared with traditional mushroom-like electromagnetic band gap (EBG) and coplanar EBG, the proposed nested CSRRs structure only need to be partially etched on the power plane and is easy to be fabricated, while the performance...
This paper presents a two stage low noise chopper amplifier for integrated angular acceleration sensor signal processing circuit which consists of amplifiers, phase-locked loop and automatic gain control. Capacitor feedback amplifier circuit is one of the most suitable for CMOS technology however capacitor amplifier with chopped op-amp has poor low frequency performance because of parasitic resistive...
In this paper the common-mode noise generation mechanism and its suppression is presented for the hard-switched isolated full-bridge forward topology. Due to the extensive interleaving of primary and secondary windings, such transformers exhibit large inter-winding capacitance which is the well-known cause of large common-mode noise current in the converter. Therefore, the effect of this large coupling...
This paper describes a new 2-1 cascaded hybrid sigma delta modulator where the discrete time filter is realized with fully differential current conveyor. The hybrid convertor, which is a combination of an analog integrator and two digital integrators, offers an increased dynamic range, helps make the resulting high-order sigma delta modulator stable and reduce power consumption comparing with discrete...
The hybrid fully differential second order Gm — C lowpass filter constructed from an operational transconductance amplifier and a PMOS source follower is presented in this paper. This proposed LPF is simulated using 0.35 μm standard CMOS process and consumes 9.19 nW at 1.5 V power supply for 100 Hz bandwidth. The bandwidth of this proposed LPF is tunable from 10 Hz to 1 kHz. The benchmarks between...
The proposed method uses a simultaneous pre-charging schema to sensing capacitance change on the sensing pad. In order to compensating the unstable sensing value due to the changing in power supply, an extra reference capacitor pair is adding to the schema. With simultaneous pre-charging schema, all of the sensing capacitors (Cs) including reference capacitors are charged to same voltage level before...
A fully-digital True Random Number Generator (TRNG) measures the frequency difference between two free-running ring oscillators, or in other words the beat frequency, to extract random frequency jitter. For generating a continuous stream of random bits with a high entropy level, the lower significant bits meeting the NIST randomness criteria are concatenated. The generation efficiency is further improved...
This paper presents a biopotential analog front-end (AFE) IC for measuring electroencephalogram (EEG). The AFE is based on the AC-coupled chopper stabilized instrumentation amplifier architecture to achieve the low noise. To increase the input impedance, the capacitive input impedance boosting loop (CIIBL) is proposed. The CIIBL forms a positive feedback loop between input and output of the instrumentation...
Currently, there is immense incentives-driven research, in the automotive industry to develop Plug-In Electric Vehicles (PIEVs) to reduce the green-house gas emissions and to comply with the Kyoto accord. Isolated High frequency AC-DC converters are a major component to transfer power from utility mains to the traction battery packs which store energy for the EV motors propulsion. The front-end AC/DC...
We present measurements from a prototype array of superconducting kinetic inductance detectors optimized for 150 GHz radiation and commercially fabricated from 20 nm aluminum films on silicon wafers.
A configurable three-level sigma-delta ADC for both DC measurement and audio conversion is implemented in a 40 nm CMOS process. It employs a switch-capacitor level shifter to increase the DC input range. Dynamic Element Matching (DEM), typically used in traditional multilevel feedback DAC, is avoided by setting proper common-mode (CM) voltage. Using a time-sharing technique, the three-level quantizer...
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