Serwis Infona wykorzystuje pliki cookies (ciasteczka). Są to wartości tekstowe, zapamiętywane przez przeglądarkę na urządzeniu użytkownika. Nasz serwis ma dostęp do tych wartości oraz wykorzystuje je do zapamiętania danych dotyczących użytkownika, takich jak np. ustawienia (typu widok ekranu, wybór języka interfejsu), zapamiętanie zalogowania. Korzystanie z serwisu Infona oznacza zgodę na zapis informacji i ich wykorzystanie dla celów korzytania z serwisu. Więcej informacji można znaleźć w Polityce prywatności oraz Regulaminie serwisu. Zamknięcie tego okienka potwierdza zapoznanie się z informacją o plikach cookies, akceptację polityki prywatności i regulaminu oraz sposobu wykorzystywania plików cookies w serwisie. Możesz zmienić ustawienia obsługi cookies w swojej przeglądarce.
A flash analog-to-digital converter (ADC) using multiplexers (MUXs) to reduce the number of preamplifiers and comparators is reported. A traditional N-bit flash ADC requires 2N−1 preamplifiers and comparators while the proposed ADC only needs 2(N−3)+2 preamplifiers and 2(N−2)+1 comparators. For a 6-bit resolution, the proposed ADC requires a reduce number of preamplifiers and comparators by 84% and...
This paper presents the design and characterization of an electronic sensing system interfaced with a high-density flexible biomechanical ground reaction sensor array (GRSA). The prototype system can be incorporated into a personal boot heel to measure real-time ground force shear strain and sole deformation associated with a human bipedal locomotion thus providing zero-velocity correction to an inertial...
We developed a Wide IO DRAM controller chip with Through Silicon Via (TSV) technology. Test circuitry is embedded in the micro-IOs placed between the fine pitch TSVs which can reject TSV connectivity failures prior to stacking process. In order to reduce Vmin degradation induced by 512 DQs simultaneously switching noise, we introduce a package-board impedance optimization method utilizing a full digital...
This paper presents different design considerations for the receiver front-end (RXFE) in low-power, high-speed data links. Specifications for the RXFE are defined and explained in detail, including their impact on the overall link performance. Based on these specifications, low-power RXFE topologies are then analyzed to illustrate the design and performance tradeoffs. Techniques to properly characterize...
The combination of increasing working frequencies and shrinking transistor size following the Moore's Law, dictate the design and fabrication of complex System-on-Chip (SoC) designs, where the digital processing core, SRAMs and embedded flash memories, analog IPs and I/O cells, are integrated onto the same die. Therefore, noise integrity has become a critical concern for high-speed SoC designers,...
High frequency transformers are one of the essential building blocks to provide galvanic isolation for power converters. Due to the switching nature of the converter, electromagnetic compatibility (EMC) of these converters is an essential requirement, to ensure not only its own operation but also the safe and secure operation of surrounding electrical equipment that are connected to same power distribution...
In this paper, a novel technique to reduce the common mode noise of bended differential transmission lines is proposed. To this end, open circuited transmission lines are employed to compensate the undesirable capacitance of the bends. This method can remarkably decrease the differential to common mode conversion ratio in a very wide frequency range while offering an acceptable level of input return...
With the decrease of the digital circuit noise tolerance and the timing margins tolerance. The simultaneous switching noise (SSN) of Power ground plane become a major bottleneck for high speed design. The existing method of suppressing SSN exist their short comings. In this paper, the new method combined electromagnetic band gap(EBG)with decoupling capacitors is put forwarded to use design to suppress...
The paper introduces specific ways of optimizing Proportional-Integral-Derivative (PID) type closed-loop Microelectromechanical System (MEMS) accelerometer system performance under fixed boundaries. Parameters tuning is applied to enhancing loop gain, under which configuration the tested Total Noise Equivalent Acceleration (TNEA) is around 3.2ug-√Hz @10Hz with bandwidth over 200Hz. This result is...
A monolithic accelerometer design with zero-g calibration with TSMC 0.18 μm mixed-signal 1P6M process is presented. On-chip digital offset calibration enables compensation of random mechanical offset in the sensor due to process variation. The maximum 21 fF capacitance mismatch can be calibrated. The simulation results show that the whole system have 452.1 mV/g sensitivity. The power consumption is...
A new sensing configuration based on the direct use of the metal input pad of a dedicated CMOS amplifier as a conductive substrate electrode for nanoscale high-performance electrical measurement with a standard conductive AFM is proposed and experimentally validated. Combining the state-of-the-art performance of an integrated current preamplifier (5MHz bandwidth, 14fA/sqrt(Hz) noise at 1MHz) with...
The digital closed-loop quartz flex accelerometer (DCLA) can acquire higher measuring accuracy, which plays an important role in the inertia navigation system while noise is one of the main factors to restrict the precision of DCLA. In this paper, the working principle and noise characteristics of DCLA are introduced and analyzed. According to the system mathematical transfer function and equivalent...
In this paper we present a new asynchronous readout technique designed for a single element infrared detector (SWIR HgCdTe APD). This circuit aims to perform photon counting on a hybridized detector at a cryogenic temperature for an atmospheric LIDAR (LIght Detection And Ranging) application. Accordingly, for the most important specifications, we obtain a very low input referred noise generated by...
AC/DC-DC/DC has been widely used in switched-mode power supply (SMPS). In this paper, the MM EMI coupling and suppression mechanisms of this type of the flyback converter will be given and its effects on DM capacitor will also be elaborated. Planar DM capacitor design examples including the theoretical and analysis of the flyback MM EMI will be used. Simulation results based on Saber will be carried...
A design methodology of reconfigurable distributed low noise amplifier (RDLNA) dedicated for wireless home communications operating from 0.8GHz to 11GHz is presented in this paper. This RDLNA is suitable to operate in two different operation modes: low power consumption mode and high performance mode. The used technology is 0.15μm InGaAs Active Layer pHEMT Process provided by TRIQUINT. The circuit...
This paper describes noise analysis for near-field intra-body communication, in which the human body is the transmission medium. In this type of communication system, the transmission line's impedance balance between the signal and the ground line is extremely degraded. Such a system is affected by large common-mode noise from various kinds of electronic equipment. Impedance balance deteriorates as...
A two-stage charge sensitive amplifier architecture suitable for semiconductor radiation detector with large capacitance is proposed. The integration capacitor of the first stage can be made large to reduce gain sensibility to detector capacitance without any stability problem. Each stage uses a self-biased MOS transistor to discharge the integration capacitor. The self-bias circuit tracks process,...
A low-noise readout integrated circuit, comprising a charge sensitive amplifier, a pulse shaper with baseline holder, a peak detector and an A/D converter, is presented. The designed IC quantifies optical response of a large-area epitaxial photodiode integrated on a body of a semiconductor scintillator. The input transistor size and the time constant of the shaper are optimized to obtain a minimum...
A three-stage common-source low noise amplifier (LNA) is designed in a 65 nm LP CMOS process. Basically, at mm-wave frequency the Miller capacitance degrades the amplifier performance dramatically. To address these issues, a transformer based neutralization technique is used. With the proposed technique, simulations show that the circuit achieves a gain of 22 dB along with a 1-dB bandwidth of 4 GHz...
This paper presents the design and implementation of a variable bandwidth amplifier intended for ultra-low-power biomedical implants in 65nm CMOS, providing tunable gain-bandwidth in three modes: 0.9 MHz, 1.7 MHz, and 2.3 MHz with consistent 56 dB DC gain. The amplifier consumes 180nW static power in the lowest bandwidth mode, and consumes 315 nW static power in the full bandwidth mode with an 8 pF...
Podaj zakres dat dla filtrowania wyświetlonych wyników. Możesz podać datę początkową, końcową lub obie daty. Daty możesz wpisać ręcznie lub wybrać za pomocą kalendarza.