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This paper reports on the component reliability improvement activities undertaken as part of the European Space Agency (ESA) GREAT2 project, culminating in the first in-orbit demonstration of an X-band telemetry transmitter using European sourced GaN technology.
This paper presents an overview of state-of-the-art simulation methodologies to investigate statistical effects associated with charge trapping dynamics and their impact on the reliability projection in decananometer MOSFETs. By means of novel 3-D Kinetic Monte Carlo TCAD reliability simulation technology we tracks the time dependent variability associated with granular charge injection and trapping...
The demand for highly scalable and low power memory has led to research in emerging technologies and devices. Among these devices, memristors has attracted increased attention as being a promising storage device. However, due to its nano-scale size it faces various types of reliability issues. In this study, we have reviewed the memristive mechanisms and reliability concerns existing in memristor...
New architectures introduction succeeded in reducing the device performances dispersion in scaled transistors, but as a consequence the relative importance of oxide reliability increased. In this work we present original results of charged interface traps impact on bulk, FDSOI and Fin FETs performances. Traps time constants are analyzed and recoverable and permanent degradation proportions are derived...
The tight coupling between the nuanced physics of silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) and the circuits in which they are utilized in many ways represents the “final frontier” for research in technology optimization, device physics, compact modeling, circuit design, and system implementations. As relevant examples of the inherent complexities associated with such “device-to-circuit...
For development of digital circuits in deep submicron, that are widely used in communication systems, vulnerability to soft error has become a critical consideration. Also with increasing complexity and number of transistors, energy consumption increases significantly. Transition to sub-threshold supply voltage regions is a popular way to remedy this issue. We address these two issues with our solution...
Advanced multifunctional computing systems realized in forthcoming technologies hold the promise of a significant increase of the computational capability that will offer end-users ever improving services and functionalities (e.g., next generation mobile devices, cloud services, etc.). However, the same path that is leading technologies toward these remarkable achievements is also making electronic...
The reliability of digital circuits designed in Schottky Barrier Carbon Nanotube Field Effect Transistor (SB-CNTFET) technology is investigated in this paper. We discuss factors that affect the height of the Schottky barrier and as a consequence the performance of circuits in SB-CNTFET. We then present a transistor-level analysis of reliability. The analysis is performed first for an inverter and...
In order to capture the effect of dependent failures that could arise due to the various transmission protection system response scenarios on power system reliability, complex Markov models or fault trees combined with event trees are typically employed in the predictive reliability studies. A unique approach utilizing minimal cutsets (MC) and the approximate methods of system reliability evaluation,...
As fabrication technology scales towards smaller transistor sizes, lower critical charge, and higher operating frequencies, single-event radiation effects are more likely to cause errant behavior in multiple, physically adjacent devices in modern integrated circuits (ICs). In order to increase future system reliability, circuit designers need greater awareness of multiple-transient charge-sharing...
The following topics are dealt with: diodes; IGBT; GaN devices;SiC devices; superjunction devices; wide bandgap power devices; packaging; power MOSFET; reliability; LV power IC; HV power IC; gate drivers and digital isolators.
We propose a new dual-level fault injection method for evaluating combination effect of single event upsets (SEUs) and single event transients (SETs). The proposed interaction method allows collaborative simulation on register-transfer level (RTL) and gate level. Conventional fault injection methods or fault model techniques typically aim at SEUs or SETs, rather than the combination of SETs and SEUs...
This paper demonstrates the advanced 300mm 0.13μm BCD platform with high flexibility. This platform brings about the various combinations from ten kinds of device options and three kinds of wiring options. Especially, for DMOS which plays an important role on the BCD platform, the best in class low Rdson is realized on Si-bulk. Furthermore, the highly reliable Flash memory cell is embedded on the...
Reconfigurable hardware platforms, such as Field Programmable Gate Arrays (FPGA), are being increasingly used in diverse embedded applications. These platforms often use high-density memory array, which suffer from variation-induced parametric failures. Such failures lead to incorrect operation and hence, loss in output quality for many signal processing applications. In this paper, we propose a preferential...
Spread spectrum time domain reflectometry (SSTDR) has been applied to a live PV inverter circuit to measure impedance variations caused by natural degradation in switching devices (MOSFET), and this method was applied without altering the normal operation of the circuit. Therefore, the proposed technique is able to perform condition monitoring - the state of health of the inverter. The experimental...
The demand for power electronic systems to operate in harsh environmental conditions has increased over the past 20 years. These environments include those relating to deep oil-well drilling, automotive and aerospace applications. The miniaturization of the power module along with higher power densities have created elevated stress levels on ancillary subsystems, specifically the control circuitry...
As technology feature sizes shrink, aggressive voltage scaling is required to contain power density. However, this also increases the rate of transient upsets -- potentially preventing us from scaling down voltage and possibly even requiring voltage increases to maintain reliability. Duplication with checking and triple-modular redundancy are traditional approaches to combat transient errors, but...
As CMOS feature sizes are shrinking, manufacturing defects are becoming a growing concern in micro and nanoelectronics. This work deals with defect tolerance in FPGAs that are surely affected by technology downscaling. In this paper, we are interested in enhancing the defect tolerance of a switch box in a mesh of clusters FPGA, while trying to reduce the hardening cost. First, we had to spot, among...
Most of the applications require hard real time signal/data processing potentiality for which fast and dedicated VLSI architectures are the best solution. But designing such circuits lead to high occurrences of failure in the system. Hence there is a critical need for fault tolerance techniques for VLSI designs to increase the reliability of the system. Redundancy techniques are implemented widely...
The NMOSFET-only pass gates used in some digital CMOS applications, such as the Field-Programmable Gate Arrays (FPGAs), are apparently vulnerable to Positive Bias Temperature Instability (PBTI). Here we discuss the impact of PBTI frequency and workload on high-k/metal-gate NMOSFETs in terms of Capture-and-Emission Time (CET) maps and quantitatively explain the degradation of our test circuit. From...
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