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A window delay-line analog-to-digital converter (ADC) with programmable resolutions for digitally-controlled switch-mode power supplies (SMPS) used in low-power portable applications is proposed in this paper. Due to its simple, low-power architecture and small silicon area, this ADC can be fully integrated with a digital controller. The proposed ADC quantizes the output converter voltage within a...
Incast applications have grown in popularity with the advancement of data center technology. It is found that the TCP incast may suffer from the throughput collapse problem, as a consequence of TCP retransmission timeouts when the bottleneck buffer is overwhelmed and causes the packet losses. This is critical to the Quality of Service of cloud computing applications. While some previous literature...
Mitigation of radiation effects is one of the major problems for space-borne computing platforms. The presented work proposes an approach for building reliable, hardware fault adaptive stream processing platforms for space applications. The proposed concept is based on architecture-to-fault adaptation by run-time hardware reconfiguration. The concept assumes representation of system components in...
As the demand for multimedia traffic via satellite increase, quality of service (QoS) management becomes more crucial, especially for the effective utilization of on-board switching capabilities of multi-beam satellite system. For multimedia services, parameters related to different requirements need to be evaluated in terms of delay, jitter, blocking probability and burstiness. This paper is on the...
A heterogeneous network, where a switched Ethernet backbone interconnects several existing CAN buses via bridges, is a promising candidate to build a large scale network. For real-time applications, deterministic communication is a key issue. A worst-case delay analysis on such a network has to deal with heterogeneity properties, such as different bandwidths, scheduling policies and bridging strategies...
As the number of processing elements in the future Networks on Chip (NoC) increases from multi-cores to many-cores, the role of the interconnection communications becomes more critical. The number of cores on a System on Chip (SoC) will reach thousands in the near future as predicted by the International Technology Roadmap for Semiconductors (ITRS). Currently, NoC interconnections are mostly implemented...
Nowadays, the multi-core platforms have become the de-facto solution to cope with the rapid increase of system complexity and energy consumption. Additionally, the dynamic power management (DPM) and the dynamic voltage and frequency scaling (DVS) are two well-established techniques to adjust the trade-off between the system performance and power consumption during runtime. However, in the context...
Service providers are experiencing a challenge that is caused by the explosive growth in demand for high-speed connections to and across metropolitan, regional and core networks. Operators are under pressure to increase the capacity of their networks to meet these ever growing requirements. To improve service agility and network efficiency and reduce costs throughout their entire infrastructures,...
This work addresses the applicability of a switched queuing network as the sole communication network in an aircraft cabin, and proposes an algorithm based on a mixed-integer program to determine hard bounds for the end-to-end delay. These hard bounds guarantee mandatory performance bounds for safety-relevant functions in the aircraft cabin, such as audio announcements or smoke detection. Techniques...
Multi-stage buffered Clos-network switches suffer from out-of-sequence packet forwarding. This paper proposes a three-stage memory memory memory (MMM) Clos-network switch, called the MCS switch, which provides in-sequence packet forwarding while maintaining high throughput. The proposed MCS switch adopts the oldest-cell-first selection for arbitrations at the first and second stages and an iterative...
As CMOS technology has scaled, supply voltage has dropped, chip power consumption has increased, and clock frequency has increased, the effects of jitter become critical and jitter budget gets tighter. Jitter can be decomposed into several components, each having specific sets of characteristics and root causes. This paper presents a short review of jitter fundamentals including a discussion of the...
Delay of voice end user (DOVE) is a promising technique in enhancement of carried traffic of both voice and data of a network. Several literatures are available for DOVE in voice data integrated services. In this paper the same concept is applied in micro-macro cellular system where DOVE is applied at the end of user of micro cell and macro cell separately for comparison of different traffic parameters...
Low leakage power switch is proposed to allow saving in power dissipation of the Network on Chip (NoC). The proposed NoC switch employs power supply gating to reduce the power dissipation. Two power reduction techniques are exploited to design the proposed switch. Adaptive Virtual Channel (AVC) technique is proposed as an efficient technique to reduce the active area using hierarchical multiplexing...
This paper describes improvements to the technique of velocity selective recording (VSR) in which multiple neural signals are matched and summed to identify excited axon populations in terms of velocity. The signals are acquired using a multi-electrode cuff (MEC) which is now available as a component for use in implantable neuroprostheses. The improvements outlined in the paper involve the replacement...
In this paper, we present a technology mapping and clustering tool for leakage power reduction in FPGAs with programmable, dual-VT logic blocks. The use of Reverse Back Bias (RBB) circuit techniques is recognized as one of the more promising strategies in mitigating leakage power, a critical problem in circuits deploying deep submicron process technologies. FPGAs with the ability to adjust fabric...
This research work has been done in designing and developing a Novel Distribution Automation System (DAS) in an open loop customer side distribution system. The research has utilized an automation techniques in both hardware and software environment using a communication network and embedded controllers along with power meters which has utilized the possible best solution for the fault operation and...
Flash data dissemination transmits time-critical data to distributed receivers in a timely manner, which is widely used in many mission-critical applications. However, existing flash data dissemination approaches fail to guarantee the timely transmission due to the unpredictability of the dissemination process. Overlay routing has been widely used as an efficient routing primitive for providing better...
This paper describes implementation issues for high speed 2-step-flash analog-to-digital converters (ADCs) without digital correction. A novel implementation for a multiplying digital-to-analog converter (MDAC) is described, which is a sample-and-hold amplifier, which includes a DAC, residue amplification and correlated double sampling (CDS), thereby omitting two-phase compensation differences. No...
A Hierarchical Torus Network (HTN) is a 2D-torus network of multiple basic modules, in which the basic modules are 3D-torus networks that are hierarchically interconnected for higher-level networks. Three deadlock-free adaptive routing algorithms called link-selection, channel-selection, and a combination of link-selection and channel-selection was proposed for the efficient use of physical links...
For the rotary inverted pendulum system in network control system, a variable structure control method with time-varying sliding surface of delay compensation is proposed. The inverted pendulum system model was established and analyzed, and the sliding surface and sliding mode control law design process were shown. Through using MATLAB/Simulink control system design and simulation tools to analyze...
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