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A new structure of comparator circuit based on a pair of complementary floating-gate (FG) MOS transistors is introduced in this paper. Our main design purpose is to focus on low complexity structure and low operating supply voltage. The comparator comprises two stage amplifiers: differential input stage and gain stage. Simulation results from Hspice on 0.25 mum TSMC CMOS technology and 1.5 V power...
This paper presents a Resolution Adaptive Flash A/D Converter design and its performance. To achieve high speed, the proposed A/D converter utilizes Threshold Inverter Quantization technique replacing conventional analog comparators with digital comparators. The replacement results in a faster digital conversion and a reduction of the analog nodes in the ADC. The proposed ADC is a true variable resolution...
A kind of power conversion circuit, which converts positive voltage into negative one is presented according to the principle of negative voltage charge pump, so the DC output voltage is doubled. Factors affecting the speed and accuracy of MOS switches are fully considered, and a charge pump with MOS switches working in linear region is designed, avoiding the problem of threshold voltage drop. By...
Accurate extraction of the SPICE model parameter is critical in the CMOS IC design. However, it faces difficult issues in state-of-the-art MOSFET technology. First, the gate CV parameter extraction is challenging due to small values and many extrinsic components that need to be de-embedded. Second, the systematic offset of the gate critical dimension (CD) exists between test structures and circuits,...
Simultaneous switching noise (SSN) is an important issue for the design and test and actual ICs. In particular, SSN that originates from the internal logic circuitry becomes a serious problem as the speed and density of the internal circuit increase. In this paper, an on-chip monitor is proposed to detect potential logic errors in digital circuits due to the presence of SSN. This monitor checks the...
The implementation of complex functionality in low-power nano-CMOS technologies leads to enhance susceptibility to parametric disturbances (environmental, and operation-dependent). The purpose of this paper is to present recent improvements on a methodology to exploit power-supply voltage and temperature variations in order to produce fault-tolerant structural solutions. First, the proposed methodology...
The soft-error vulnerability of flip-flops has become an important factor in IC reliability in sub-100-nm CMOS technologies. In the present work the soft-error rate (SER) of a 65-nm flip-flop has been investigated with the use of alpha-accelerated testing. Simulations have been applied to study the flip-flop SER sensitivity in detail. Furthermore, an easy-to-use approach is presented to make an accurate...
With technology scaling, vulnerability to soft errors in random logic is increasing. There is a need for on-line error detection and protection for logic gates even at sea level. The error checker is the key element for an on-line detection mechanism. We compare three different checkers for error detection from the point of view of area, power and false error detection rates. We find that the double...
With the event of nanoscale technologies, new physical phenomena and technological limitations are increasing the process variability and its impact on circuit yield and performances. Like combinatory cells, the sequential cells also suffer of variations, impacting their timing characteristics. Regarding the timing behaviors, setup and hold time violation probabilities are increasing. This article...
Current mode (CM) scheme provides suitable alternative for the high speed on-chip interconnect signaling. This paper presents a energy-delay optimization methodology for the current-mode (CM) signaling scheme. Optimization for the CM circuits for on-chip interconnects requires a joint optimization of driver and receiver device sizes, as their parameters which affect the energy-delay performance depend...
We present a generic method for analyzing the effect of process variability in nanoscale circuits. The proposed framework uses kernel and a generic tail probability estimator to eliminate the need for a-priori density choice for the nature of circuit variation. This allows capturing the true nature of the circuit variation from a few random samples of its observed responses. The data-driven, non-parametric,...
This paper introduces a novel current sense amplifier (CSA) in sub-32nm fully depleted (FD) double-gate (DG) silicon-on-insulator (SOI) technology with planar independent self-aligned gates. A new architecture is proposed which takes advantage of the back gate in order to improve circuit properties. Compared to the reference circuit, the new architecture proves to be faster (21% sensing delay decrease),...
Class D amplifiers are becoming the most feasible solution for embedded audio application. However, distortions due to the non-linear nature of switching stage are the main drawback for this amplifier topology. This paper discusses the design and implementation of high fidelity audio class D using sliding mode control scheme. This design method proves to be a cost effective solution for industrial...
This paper presents an analytical modeling of ballistic and quasi-ballistic transport, implemented in Verilog-A environment and used for circuit simulation. Our model is based on the Lundstrompsilas approach and uses an expression of the backscattering coefficient given by the flux method. The model takes also into account short channel effects and tales into account the effects of different scattering...
In this paper, a 12-bit 50MHz Pipelined Low-Voltage ADC is presented, which consists of 8-stage-pipelined low resolution ADCs and a 4-bit flash ADC. Several critical technologies are used to guarantee the resolution and high sampling and converting rate such as 1.5bits per stage conversion, digital correction logic, gain-boosted telescopic OTA and so on. Finally the whole system is taped out in SMIC...
A propagation delay model of a short-channel CMOS inverter is reported, which considers input slope effects for timing verification by semi-empirical coefficients. Model calculations which demonstrate the source-drain series resistance effect show good agreement with SPICE MOS level 3 simulations.<<ETX>>
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