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A comma detection and word alignment circuit is proposed for a 6.25-Gb/s SerDes. In order to achieve a high speed, a new architecture of combined parallel and pipelined is employed. Based on the proposed structure, a high speed comma detector is implemented using 0.18im CMOS technology. Post simulation result indicates that the circuit can operates up to 770MHz with a power consumption of 10.8 mW...
A novel quaternary D-flip-flop is proposed by using dynamic source-coupled logic (SCL) for high performance processing element in VLSI system. Its key components, the threshold detectors, are based on differential-pair circuit (DPC). The combination of multiple-valued source-coupled logic and differential-pair circuit makes it low power and more compact. The performance is evaluated by HSPICE simulation...
A quick and easy laser experiment for photocurrent induced upset investigations has been described as a preliminary test method for SEE experiments. In order to focus a laser beam on a desired transistor in complex LSI circuits, novel test circuit structures using selectively metal-covered transistors have been proposed. Photocurrent induced upsets have been successfully observed in a target CMOS...
In this work we present the results of full Geant4 and FLUKA simulations and comparison with dosimetry data of an electron LINAC of St. Maria Hospital located in Terni, Italy. The facility is being used primarily for radiotherapy and the goal of present study is the detailed investigation of electron beam parameters to evaluate the possibility to use e-LINAC (during time slots when it is not used...
A fully differential (FD) voltage buffer suited to low-voltage operation and able to operate over a wide voltage range is presented. The buffer core is based on a FD difference amplifier including bulk-driven MOS transistors as input devices. The common-mode (CM) component of the buffer output voltage is controlled by means of a bulk-driven CM feedback (CMFB) network that features an extended operating...
In this paper, we present a new seizure detection algorithm and the associated CMOS circuitry implementation. The proposed low-power seizure detector is a good candidate for an implantable epilepsy prosthesis. The device is designed for patient-specific seizure detection with a one variable parameter. The parameter value is extracted from a single seizure that is subsequently excluded from the validation...
A 16 × 16 staring imaging array was implemented in a 0.15-µm standard CMOS technology for terahertz detection in the range of 0.8 THz to 1.5 THz. Each pixel is composed of an antenna, a FET detector, and its readout electronics (a current integrator) so that the pixel signals of the whole matrix can be acquired simultaneously. The current integrator employs a 129-dB operational amplifier implementing...
A new architecture for Positron Emission Tomography visible-light detectors is presented. The architecture is based on mini-SiPMs (arrays of 32 SPADs), which are locally digitized. With this architecture we expect to achieve a high fill factor while still performing an early enough analog-to-digital conversion so as to avoid interconnect parasitics common of standard SiPMs. The detector is implemented...
This work is concerned with the design of two different analog channels for hybrid and monolithic pixels in view of applications to the vertex detector at the SuperB Factory. The circuits have been designed in a 130 nm CMOS, vertical integration technology, which may provide some advantages in terms of functional density and electrical isolation between the analog and the digital section of the front-end...
The characterization of a 10×10-SPAD detector module fabricated in a 0.35µm High Voltage CMOS technology is presented. The detector is designed to find application in Fluorescence Lifetime spectroscopy and is capable of performing lifetime measurement by using the time-gated technique. The characterization explores the dark count distribution, the detector dynamic range and the gating performances...
We present a high precision Time-to-Digital Converter (TDC) architecture suitable for multi-channel implementations in monolithic arrays of single-photon avalanche diode (SPAD) detectors aimed at TCSPC applications (like FLIM, FCS, FRET), but also at photon timing and direct TOF measurements for 3D ranging applications (e.g. in LIDAR systems). A “smart-pixel” with a SPAD detector, an analog sensing...
In this paper, the design of a new low-power low-noise charge-sensitive amplifier (CSA) is presented. The proposed CSA is intended for capacitive sensor readout circuits such as interface circuits for solid-state detectors used in medical imaging and X-ray spectroscopy. A comprehensive noise analysis of readout systems that consist of a CSA followed by an RC-CR pulse shaper is presented. To facilitate...
We report on the study of the enhancement of responsivity and properties of low-frequency noise in silicon 0.25 µm CMOS transistor-based detectors for terahertz radiation under applied dc source-to-drain current. We find that at signal modulation frequencies above 50 kHz the signal-to-noise ratio becomes independent from applied current, whereas the responsivity of detectors can be enhanced up to...
This paper presents the design of a CMOS RF RMS power detector for an Automatic Impedance Matching System. The power detector requirements for this application, in terms of dynamic range, resolution, settling time and power consumption, are met by distributing the dynamic range over three power detection units. The appropriate unit is dynamically selected based on the input power range. The output...
An on-chip Frequency-Selective-Surface (FSS) integrated with a Proportional-to-Absolute-Temperature (PTAT) circuit for detecting infrared wave in CMOS process is presented. The slot-type FSSs with different slot length reveal different transmission properties. The power absorbed by the chip is analyzed by electromagnetic and thermal simulation software. The measurement results at 28.3 THz show good...
A very-front-end electronics has been developed to fulfil requirements for the next generation of electromagnetic calorimeters. The compactness of this kind of detector and its large number of channels (up to several millions) impose a drastic limitation of the power consumption and a high level of integration. The electronic channel proposed is first of all composed of a low-noise Charge Sensitive...
Despite a continuously increasing demand, neutron electronic personal dosimeters (EPDs) are still far from being completely established because their development is a very difficult task. A low-noise, ultra low power consumption CMOS pixel sensor for a future neutron personal dosimeter has been implemented in a 0.35 μm CMOS technology. The prototype is composed of a pixel array for detection of charged...
In this paper, an IgE antigen concentration measurement system using a frequency-shift readout method for a two-port FPW (flexural plate-wave) allergy biosensor is presented. The proposed frequency-shift readout method adopts a peak detecting scheme to detect the resonant frequency. A linear frequency generator, a pair of peak detectors, two registers, and an subtractor are only needed in our system...
We present a fully integrated, Single Photon Avalanche Detector (SPAD) using only standard low-voltage (1.8V) CMOS devices in a 0.18µm process. The system requires one high-voltage AC signal which alternately reverse biases the SPADs into avalanche breakdown and then resets with a forward bias. The proposed self-quenching circuit intrinsically suppresses after-pulse effects, improving signal to noise...
This paper presents a high-speed, low-power and wide signal swing differential dynamic amplifier using a common-mode voltage detection technique. The proposed dynamic amplifier achieves a 15.5 dB gain with less than 1 dB drop over a signal swing of 1.3 Vpp at an operating frequency of 1.5 GHz with a VDD of 1.2 V in 90 nm CMOS. The power consumption of the proposed circuit can be reduced linearly with...
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