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In High speed operations the duty cycle of the clock signal is to be calibrated at 50%. But the variations in process, voltage and temperature (PVT) influences the duty cycle and make it difficult to calibrate the duty cycle at 50%. To overcome this deviation Pulse width control loops (PWCLs) are used. This work presents a highly reconfigurable and fast locking all digital pulse width control circuit...
Ongoing research in graphene-based nano-transceivers and nano-antennas points to the Terahertz (THz) band (0.1-10 THz) as the communication frequency range for nano-devices. Femtosecond-long pulse-based modulation schemes have been proposed to enable ultra-broadband communication among nano-devices. One of the main challenges with ultra-high-speed pulse-based communications is the need for tight symbol...
A novel 8Gbps, 4:1 transition aware multiplexer (MUX) is proposed. The multiplexer core is basically a self-toggling TSPC flip-flop, which is deactivated when no data transition is detected. The high speed serial data is regenerated by gating the triggered clock. It combines the advantages of data retiming to eliminate deterministic jitter. Besides, the short clock-to-Qb delay enables high speed multiplexing...
An adaptive circuit is proposed to adjust CDR loop bandwidth based on different jitter spectral profile for better jitter performance. The preventional lock detector (PLD) is employed to achieve better jitter suppression ability without jitter tolerance (JTOL) degradation. The proposed circuit enhances the jitter suppression by 14.14 dB at an 8-MHz sinusoidal jitter source. This adaptive block is...
We present the new TDAQ system designed for the upgraded MEG experiment. It is an assembly of three new boards in a dedicated crate. The system foundation is on the so called WaveDREAM board with DAQ and trigger capabilities accompanied by trigger concentrator boards, to collect information from the detectors and perform real time event reconstruction, and data concentrator boards for DAQ purposes...
This paper describes a 960×960 Frame Store Fast Charge-Coupled Device (CCD) x-ray detector being used for x-ray photon correlation spectroscopy (XPCS) at the Advanced Photon Source (APS) on the 8-ID-I beam line. The detector is typically operated in either the 960 × 960 pixel mode at 100 frames per second (fps) or in the 960×90 pixel mode at 1000 fps. The vacuum subsystems consist of a top board with...
SAMPIC is a Waveform and Time to Digital Converter (WTDC) multichannel chip. Each of its 16 channels associates a DLL-based TDC providing a raw time with an ultra-fast analog memory allowing fine timing extraction as well as other parameters of the pulse. Each channel also integrates a discriminator that can trigger itself independently or participate to a more complex trigger. After triggering, analog...
Super-Kamiokande (SK) is a 50-kiloton Water Cherenkov detector and. it is able to detect a large number of supernova burst neutrinos with its large target mass.
The integration of a variety of IP cores into a single chip to meet the high demand of new applications leads to many challenges in timing issues, especially the interface between different clock domains. Globally Asynchronous, Locally Synchronous (GALS) approach addresses these challenges by dividing a chip into several independent subsystems working with different clock signals. In multi-synchronous...
In this paper a clock and data recovery circuit (CDR) with modified D latch is designed meeting the standards of 10 Base-KR standard backplane. The designed circuit employs dual loop architecture in 0.18μm UMC CMOS technology. The simulated results indicate a phase noise of voltage controlled oscillator (VCO) as −173.782dBC/HZ, VCO gain of 350MHz/V while consuming 85mW from 1.8V supply. LC oscillator...
Data races are one of the most common problems in concurrent programs. As SystemC standard allows nondeterministic scheduling of processes, this leads to data races. Hence, different executions of the same concurrent program may lead to unexpected results due to race conditions. We develop a hybrid dynamic data race detection algorithm for SystemC/TLM designs that adopts the well-studied dynamic race...
A 12.5 Gb/s half-rate clock and data recovery (CDR) circuit is described. The CDR uses a half-rate linear phase detector (LPD) which minimizes the number of latches required. To correct for static phase offsets (SPO) that inevitably result from variations in analog circuit parameters, a calibration scheme is used on startup. Measured high-frequency jitter tolerance is improved by up to 0.2 UIpp through...
A continuous-rate CDR based upon a digital dual delay/phase locked loop is reported. This CDR is implemented in 0.13μm CMOS and operates from 6.5Mb/s to 11.3Gb/s. It exceeds all SONET jitter specifications from OC-3 to OC-192, with random jitter of 452fs at 9.95Gb/s. The die area is 2×2mm2, and is implemented in a 24-pin LFCSP.
The Readout Integrated Circuit (ROIC) consists of charge integration, charge to voltage conversion, Pixel voltage multiplexing, signal transfer and amplification stage. The control circuit manages all the sequential events from charge integration to amplification stage. The large dynamic range requirement is the most challenging aspect in modern CMOS process. The infrared (IR) detectors looks for...
This paper presents a low-power 28 Gb/s PLL-based clock and data recovery circuit in 65 nm CMOS technology. The artificial LC transmission line technique is proposed to be used in the full-rate bang-bang phase detector to reduce the number of D-latches and save power consumption by 42.8% compared with the conventional phase detector design. By using the transmission line technique, the retiming circuit...
Energy-efficiency is among the most important goals of the current IC industry. To achieve this goal each subcomponent of a chip must be optimized for energy). Even though a tremendous amount of research has been dedicated to optimizing floating-point multipliers (FPM) for better performance, efforts are continuously being made to further enhance them, indicating their importance in the computing...
This paper describes a fast-settling all-digital PLL with a low-power TDC based on retimed reference clock and a lock detector focused on monitoring a toggling phase error. With the intention of reducing power dissipation, the proposed TDC employs the low-rate reference (CKfref) and retimed reference (CKfros) clocks to measure the fine fractional phase error between the low-rate reference (CKfref)...
Improving energy efficiency in network equipments and data centers is becoming an increasingly important research topic. Recent researches on energy saving for green data center aim to solve problem: How to make the energy consumption is proportional to the actual traffic on the network. In this paper, we present a design aimed at reducing the power consumption for Openflow Switches while guaranteeing...
This paper presents an adaptive equalizer that converts the attenuated signal into Duobinary signaling scheme, combined with automatic Duobinary tracking technique to produce high quality Duobinary signal for simplifying the Duobinary decoding process and achieving higher data rate. The adaptive equalizer uses dual gain-mode topology that allows higher gain when the received signal is highly attenuated,...
This paper proposes Clock-RSM, a new state machine replication protocol that uses loosely synchronized physical clocks to totally order commands for geo-replicated services. Clock-RSM assumes realistic non-uniform latencies among replicas located at different data centers. It provides low-latency linearizable replication by overlapping 1) logging a command at a majority of replicas, 2) determining...
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