The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Contemporary digital systems must necessarily be based on the “System-on-Chip - SoC” concept. An interesting style for SoC design is the GALS (Globally Asynchronous, Locally Synchronous) paradigm, which can be used to implement circuits in FPGAs (Field Programmable Gate Array). Although these devices have the benefits of low-cost and short development time, there's a major drawback which is implementing...
Interpolation is a basic concept in all fields of science and technology. Calculating the neighboring weights of an un interpolated data is found. This can be done effectively by partial volume interpolation, because it produces smooth changes with small changes in transformation and improves subvoxel accuracy. Partial volume interpolator consists of multipliers as its main component. In this work,...
We propose an efficient implementation of Monte Carlo based statistical static timing analysis (MC-SSTA) on FPGAs. MC-SSTA, which repeatedly executes ordinary STA using a set of randomly generated gate delay samples, is widely accepted as an accuracy reference because of its ability to handle any timing distributions and correlations. Extremely long CPU time has been required for the MC-SSTA, which...
Thanks to recent technology advances, the exploration of the vertical dimension has been shown to be more than a dream for designers. Among those technologies, the vertical transistor has not been exploited yet. This paper describes a novel implementation of logic gates fully benefiting of nanowire-based vertical transistors embedded within the metal lines. The logic design in this technology is explored...
As fabrication process technology continues to advance, mask set costs have become prohibitively expensive. Structured ASICs can offer price and performance between ASICs and FPGAs. They are attractive for mid-volume production and offer good intellectual property security. In this paper, a structured ASIC methodology, where 2 metal- and 1 via-mask are customised, is described. The CAD tools are fully...
We show NBTI delay degradation considering variations in a 65 nm process. We evaluate these two models. The homogeneous degradation model (HDM) assumes that NBTI degradation is constant at any variation and the inhomogeneous degradation model (IDM) assume that it is larger at the fast condition. In the usual logic gates on ASICs, delay degradation becomes much smaller on IDM. Circuit design guardbands...
The Wave Dynamic Differential Logic (WDDL) offers an affective way to address Differential Power Attack (DPA). However, the effectiveness of this countermeasure is guaranteed provided the routing of both the real and complementary paths is balanced, to obtain equal propagation delays and power consumption on differential signals. This paper addresses the problem of timing unbalance. First, we propose...
Advanced Encryption Standard (AES) is one of the most common symmetric encryption algorithms. The hardware complexity in AES is dominated by AES substitution box (S-box) which is considered as one of the most complicated and costly part of the system because it is the only non-linear structure. The proposed work employs a combinational logic design of S-Box implemented in Virtex II FPGA chip. The...
This paper introduces a novel synchronous to asynchronous logic conversion tool targeted specifically for a synchronous field programmable gate array (FPGA). This tool augments the synchronous FPGA design flow and removes the clock network to implement an asynchronous control network in its place. We evaluate the timing performance benefits of the methods used to implement the asynchronous control...
This paper presents an approach to the automatic mapping of arbitrary combinational circuits to the arithmetic carry-chain structures widely available in modern FPGAs. This capability is highly valuable as it enables the utilization of these fast special-purpose structures for general-purpose logic. The described approach is both automatic and generally applicable to all carry-chain architectures...
An advantage of a RLD (Reconfigurable logic device) such as an FPGA (Field programmable gate array) is that it can be customized after being manufactured. However, there is a problem related to standby power when using it in SoC used in embedded systems. Power gating, which is one of the power reduction techniques, is difficult to use in SRAM-based RLDs because of the high overhead - data hibernation...
GPUs are becoming an increasingly attractive option for obtaining performance speedups for data-parallel applications. FPGA technology mapping is an algorithm that is heavily data parallel; however, it has many features that make it unattractive to implement on a GPU. The algorithm uses data in irregular ways since it is a graph-based algorithm. In addition, it makes heavy use of constructs like recursion...
Reconfigurability of a novel spintronics-based MOSFET; “Spin-transfer-Torque-Switching MOSFET (STS-MOSFET)” was successfully realized in the transport properties. The device showed magnetocurrent (MC) and write characteristics with the endurance of over 105 cycles. It was clarified that the read and write characteristics (i.e., MC ratio and write voltage) can be improved by choosing connection configurations...
Malicious alterations of integrated circuits during fabrication in untrusted foundries pose major concern in terms of their reliable and trusted field operation. It is extremely difficult to discover such alterations, also referred to as “hardware Trojans” using conventional structural or functional testing strategies. In this paper, we propose a novel non-invasive, multiple-parameter side-channel...
In this paper, we propose for the first time the application of ambipolar CNTFETs with in-field controllable polarities to design regular fabrics with static logic. We exploit the high expressive power provided by complementary static logic built with ambipolar CNTFETs to design compact and efficient configurable gates. After evaluating a polarity-aware logic design for the configurable gates, we...
Previously, a two-step approach to perform the cyclic redundancy check (CRC) computation in hardware was presented. In that approach, an architecture is constructed from a suitable multiple polynomial for a fixed generator polynomial and input size. In this paper, we revisit the two-step approach and suggest a modification to its architecture. First, we propose retiming the second step to the delay...
This work presents a study about FPGA interconnections and evaluates their effects on voltage-mode binary and quaternary FPGA structures. FPGAs are widely used due to the fast time-to-market and reduced non-recurring engineering costs in comparison to ASIC designs. Interconnections play a crucial role in modern FPGAs, because they dominate delay, power and area. The use of multiple-valued logic allows...
Synchronizers play a key role in multi-clock domain systems on chip. Traditionally, improvement of synchronization parameters with scaling has been assumed. In particular, the resolution time constant (tau) has been expected to scale proportionally to the gate delay 'FO4'. Recent measurements, however, have yielded counter-examples showing a degradation of tau with scaling. In this paper we describe...
Integrating DSP blocks into FPGAs is an effective approach to close the existing gap between FPGAs and ASICs. A much wider range of applications could benefit from DSP blocks if they were more versatile than those currently found in commercial devices. In this paper we propose a novel DSP block which resembles commercially available ones and yet additionally supports a wide variety of multiplier bit...
The paper deals with the characterization of sources of randomness in true random number generators aimed at cryptographic applications implemented in Field Programmable Gate Arrays (FPGA). One of the most often used source of randomness in logic devices is the timing jitter present in clock signals, generated using ring oscillators (RO). In order to estimate the entropy of the generated random bit-stream,...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.