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This paper presents a dynamic latched comparator suitable for applications with very low supply voltage. It adopts a circuit topology with a separated input stage and two cross-coupled pairs (nMOS and pMOS) stages in parallel instead of stacking them on top of each other as previous works. This circuit topology enables fast operation over a wide input common-mode voltage and supply voltage range....
In this communication, an ultra-compact I–V nanometer MOS model is used to predict the dynamic characteristics (propagation delay and rise/fall times) of CMOS inverter and more complex stacked-transistor gates. Simulations reveal typical errors within 1–3% (always less than 6%) for the simple inverter case and within 4–8% (always less than 11%) in the case of stacked-transistor gates.
This paper presents a framework to investigate the potential impact of time-dependent variability at future technology nodes. Both static statistical variability and NBTI-induced device degradation have been integrated to represent the time-dependent variability, and the impact on the performance of an ISCAS benchmark circuit in sub-35nm technologies has been studied. The BSIM4 compact models of MOSFET...
This paper treats post-silicon skew tuning for improving performance yield under various delay variations, and proposes a novel PDE tuning algorithm which utilizes only the result of setup and hold timing tests, not the result of delay measurements. Our algorithm is based on “trial-and-error” approach, and it has a proper level of robustness against the variation of each PDE characteristics. As far...
The Elmore delay has been the metric of choice for the performance driven design applications. But the accuracy of the Elmore delay is insufficient. This paper presents an accurate and efficient model to compute the delay metric of on-chip high speed VLSI interconnects for ramp inputs. The proposed delay metric is based on the distributed RC interconnect model. For optimization like physical synthesis...
With CMOS technology shrinking to nanoscale regime, the susceptibility of a single chip to soft errors increases. Hence, the critical charge (Qcrit) of circuit decreases and this decrease is expected to continue with further technology scaling. In this paper previous hardened latch circuits are analyzed and it is found that previous designs offer limited protection against soft error especially for...
Rapidly growing complexity in 3D ICs has led an increase in popularity of test methodologies based on delay testing. In this paper, we analyze the physical level design of 3-D stacked DRAM ICs with Through Silicon Via (TSV) to evaluate the propagation delay. We have performed design and electrical circuit model extraction to analyze the propagation delay in 3D DRAM ICs using the traditional 3-transistor...
Prefix computation is one of the fundamental problems that can be used in many applications such as fast adders. Most proposed parallel prefix circuits assume that the circuit is of the same width as the input size. In this paper, we present a class of parallel prefix circuits that perform well when the input size, n, is more than the width of the circuit, m. That is, the proposed circuit is an almost...
Pre-bond test has been identified as a vital step for the wafer level integration of 3-D ICs [1], [2]. The data obtained during this step can guide the subsequent manufacturing stages to improve the functional or parametric yield of the 3-D stack. The existing methods, however, do not relate directly the performance of the resulting circuits with sales revenues. More importantly, methods that consider...
Post-silicon validation, i.e., physical characterization of a small number of fabricated circuit instances before start of high-volume manufacturing, has become an essential step in integrated circuit production. Post-silicon validation is required to identify intricate logic or electrical bugs which could not be found during pre-silicon verification. In addition, physical characterization is useful...
Three-dimensional (3D) integration is a fast emerging technology that offers integration of high density, fast performance and heterogeneous circuits in a small footprint. Through-Silicon-Vias (TSVs) enable 3D integration by providing fast performance and short interconnects among tiers. However, they are also susceptible to defects that occur during manufacturing steps and cause crucial reliability...
As the technology node continues to shrink, an effective and accurate metric is essential to measure the test quality of small delay faults (SDFs), which may cause failure at circuit outputs. Owing to including gross delay fault (GDF) coverage, prior metrics cannot concentrate on the detection of SDFs. We propose a new metric, statistical SDF Coverage (S-SDFC), for differentiating SDFs and GDFs and...
The subthreshold circuit is a promising ultra-low-power solution for such applications that don't require high speed but are extremely power-stringent. The characteristic of the current under subthreshold voltage is different from the normal domain. A delay model is essential to predict the performance, analyze the variation impacts and optimize the design. This paper proposes a fast computable delay...
Recent work has shown large variations due to bias-temperature instability (BTI) at the device level, and we study its impact on the behavior of larger circuits. We propose an analytical method that is over 600x faster than Monte Carlo simulation and accurate for technologies down to 16nm, and demonstrate it on circuits with up to 68,000 transistors. Results show that the impact of BTI variability...
As a result of the evolution to nano-technology, the demand for accurate Static Timing Analysis (STA) at transistor level for high speed/high performance digital integrated circuits is increased. Despite the existence of many research attempts to resolve the timing analysis problems, (STA) remains the best solution because of the extremely fast run time and accuracy. The accurate modeling for highly...
For the current existing problems of modeling on stage different coordination, it analyzes the Ampere-second characteristic of the common DC circuit breakers, which must considers the dispersion characteristic. Through correcting the Ampere-second characteristic function by time-sharing coefficient, it can draw the Pre-acring Ampere-second curve and analyze the stage different coordination. On this...
A direct way to get the throughput of an asynchronous circuit would be through simulations. However, traditional simulation-based throughput analysis methods cannot achieve both accurate in estimates and quick in runtimes. In this paper, we propose an event-driven simulator to estimate the throughputs of asynchronous pipelines. Experimental results show the efficiency of the method.
A 6-bit passive phase shifter for S frequency band has been designed in a standard HEMT technology. A new switched-network topology has been proposed for implementing the 5.625 phase shift step which these digital bits are series with each other. We used Advanced Design System (ADS2010) to perform simulations. These digital bits will produce 64 different mode phase shift of −177.15 to +177.15 degree...
Reversible logic has become one of the most promising research areas in the past few decades and has found its applications in several technologies; such as low power CMOS, nano-computing and optical computing. Reversible logic gates are widely known to be compatible with future computing technologies which virtually dissipate zero heat. Adders are fundamental building blocks in many computational...
This paper proposes a new approach for synthesis by direct mapping of extended burst-mode asynchronous finite state machines (XBM_AFSM). The great advantage of the synthesis by direct mapping is the achieved simplicity in methodology, not demanding any knowledge about asynchronous logic concepts, hazard-free circuits and critical race theory. The synthesized XBM_AFSMs operate in mode Ib/Ob, which...
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