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Asynchronous controllers based on Asynchronous Finite State Machines (AFSM) are widely used in the control unit design of asynchronous systems. These systems can be implemented in Field Programmable Gate Arrays (FPGAs), which are a low cost design alternative. Different styles have been proposed to implement AFSMs, but all of them have limitations when implemented in FPGAs. Therefore, this paper proposes...
Controllers based on Synchronous Finite State Machines (SFSM) are widely used in the design of digital hardware and that can be implemented in Field Programmable Gate Arrays (FPGAs). A class little known and very interesting of SFSM in the FPGA platform is the SFSMs of direct output (SFSM_DO). These state machines use the output signals as state signals, thus allowing several advantages when compared...
Digital circuit design may demand critical requirements, such as power consumption, robustness, performance, etc., while being implemented in VLSI (Very Large Scale Integration). The asynchronous paradigm presents interesting features that serve as an alternative to these critical requirements. An important class of the asynchronous paradigm is the one called QDI (Quasi Delay Insensitive) circuits...
The asynchronous paradigm is an alternative to digital system design because it eliminates the problems related to the clock signal, such as clock skew, clock distribution and power dissipation of the clock. An interesting style for asynchronous design, which is familiar to designers, divides the system in an asynchronous controller with synchronous datapath. A specification known as Extended Burst-Mode...
Taking advantage of synchronous and asynchronous paradigms, a new style of design, called Globally Synchronous Locally Asynchronous (GSLA), has achieved very interesting results. In this paper, we propose a synchronous wrapper that allows the communication of “synchronous to asynchronous to synchronous” modules. Internally, the proposed interface comprises an asynchronous module. The GSLA design style...
Synchronous controllers are finite state machines (FSM) that utilize flip-flop memory elements to store states and the clock signal to synchronize their operations. In a digital system, the activity of the clock is a major source of energy dissipation. It is responsible for 15% to 45% of the total consumed energy. Reducing the activity of the clock leads to a reduction of the total energy. An interesting...
An interesting style for SoC (Systems-on-Chip) circuit design is the GALS (Globally Asynchronous, Locally Synchronous) paradigm, but its major drawback shows to be the asynchronous interfaces, especially when the GALS system is applied to a multi-point topology. The asynchronous interfaces found in literature are based on port controllers and can be called asynchronous wrappers (AW). They are responsible...
The design, implementation and comparison of Software-Defined Radio (SDR) based on GALS architectures were focused on. GALS port controllers, previously proposed for implementation in ASIC, have been redesigned for use in conventional FPGAs, eliminating the need for hard macros. A GALS architecture for SDR was proposed and validated, comprising a wrapper described in VHDL. In addition, some guidelines...
Asynchronous paradigm is another option for the project of digital systems. Several design styles can be used, where the micropipeline style is the most suitable one for FPGA platforms because it has a simpler control. It is proposed new pipeline architecture to implement asynchronous systems, in bundled-data micropipeline style, having FPGAs as target devices. One drawback of the bundled-data design...
Taking advantage of synchronous and asynchronous paradigms, a new style of design called Globally Synchronous Locally Asynchronous (GSLA) has achieved very interesting results. In this paper, we propose a high-performance interface that allows the communication of synchronous to asynchronous to synchronous modules. Internally, the proposed interface comprises an asynchronous module. The GSLA design...
Today, the design of complex synchronous digital systems shows serious difficulties relating to the global clock and to Deep-Sub-Micron MOS technology. The asynchronous design is an interesting alternative to solve these difficulties, once they do not present clock skew or distribution problems. However, the lack of tools for automatic synthesis is still a major drawback. Asynchronous Finite State...
Controllers based on Synchronous Finite State Machines (SFSM) are widely used in the control unit design of complex digital systems. These systems can present serious problems related to the global clock. In this context, the asynchronous paradigm shows interesting features that fit as an alternative for the design, despite of the difficulties of the application of asynchronous logic. An interesting...
Contemporary digital systems must necessarily be based on the “System-on-Chip - SoC” concept. An interesting style for SoC design is GALS (Globally Asynchronous, Locally Synchronous) paradigm. Currently, the major drawback in the design of a GALS system shows to be the asynchronous interface (asynchronous wrapper - AW), especially when the GALS system is applied to a multi-point topology. The AW interfaces...
This paper presents a method for an optimized synthesis of asynchronous digital systems having an FPGA as target device. The method employs the decomposition design style (data-path + controller) and uses the extended burst-mode specification to describe the controller. Asynchronous system synthesized by the method operates in “two-phase handshake protocol”, allowing a better performance. In this...
Controllers based on Synchronous Finite State Machines (SFSM) are components widely used in complex digital systems. These systems can present critical requirements, such as power consumption, robustness, performance, etc. In this context, the asynchronous paradigm shows interesting features that fit as an alternative for the design, but the lack of appropriate tools and the high difficulty of the...
Controllers based on Synchronous Finite State Machines (SFSM) are widely used in the control unit design of complex digital systems. These systems can present critical requirements, such as power consumption, robustness, speed, etc. In this context, the asynchronous paradigm shows interesting features that fit as an alternative for the design, but the lack of appropriate tools and the high difficulty...
The asynchronous paradigm has interesting features due to the lack of the clock signal and it is another option for the project of digital systems. This paradigm has several design styles, where the micropipeline style is the most suitable one for FPGA platforms, due to the simplicity of its control. In this paper, we propose a pipeline architecture to implement asynchronous digital systems, in bundled-data...
With the evolution of microelectronics, more and more high-complexity digital systems are been designed. Once the global clock signal is a main concern for synchronous systems design, asynchronous circuits seem to be an interesting alternative, once they don't present clock skew and clock distribution problems. However, the lack of tools for automatic synthesis is a major drawback. This paper proposes...
Complex synchronous digital systems can be implemented on FPGAs (Field Programmable Gate Arrays), but due to the global clock, might have problems with clock skew, performance degradation and increased of power consumed. An alternative to these designs is the asynchronous paradigm that solves the problems related to the clock. However it is difficult to design asynchronous circuits, especially in...
In contemporaneous digital systems the fetch by performance is critical, many times is accomplished through of the use of the pipeline control. In these systems the activity of the clock signal is a major energy consumer. It is responsible for 15% to 45% of the total consumed energy. Once reducing the activity of the clock signal, it is possible not only a reduction of the considered energy, but also...
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