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A 65nm self synchronous field programmable gate array (SSFPGA) which uses autonomous gate-level power gating with minimal control circuitry overhead for energy minimum operation is presented. The use of self synchronous signalling allows the FPGA to operate at voltages down to 370mV without any parameter tuning. We show both 2.6× total energy reduction and 6.4× performance improvement at the same...
This paper presents a don't-care-based synthesis technique for reducing glitch power in FPGAs. First, an analysis of glitch power and don't-cares in a commercial FPGA is given, showing that glitch power comprises an average of 26.0% of total dynamic power. An algorithm for glitch reduction is then presented, which takes advantage of don't-cares in the circuit by setting their values based on the circuit's...
Recent researches have indicated that multi-operand addition on FPGAs can be efficiently realized as the architecture consisting of a compressor tree which reduces the number of operands and a carry-propagate adder like ASIC by utilizing generalized parallel counters(GPCs). This paper addresses power and delay aware synthesis of GPC-based compressor trees. Based on the observation that dynamic power...
The correlation network of neurons emerges as an important mathematical framework for a spectrum of applications including neural modeling, brain disease prediction and brain-machine interface. However, construction of correlation network is computationally expensive, especially when the number of neurons is large and this prohibits realtime applications. This paper proposes a hardware architecture...
The SKA will be the mainstay of centimeter astronomy much of this century. It will have a sensitivity that is more than an order of magnitude greater than current radio telescopes. A second area for improved performance is the field of view (FoV). For frequencies above 1GHz a greater FoV may be achieved by placing a Phased Array Feed (PAF) at the focus of each of the SKA dishes. The design of the...
This paper presents the experimental synchronization of multiple time delay systems which are implemented on a Field Programmable Gate Array (FPGA). The obtained results verify the correctness and the feasibility of theoretical synchronization. Moreover, the digital approach here could be applied to arbitrary multi-delay feedback systems to realize secure chaotic communication.
In here we consider the problem of automatic synthesizing, from C to Verilog, circuits that are optimized to handle unpredictable latencies of memory operations. Unpredictable memory latencies can occur due to the use of on chip caches, DRAM memory modules, buffers/queues or multi-port memories. Typically highlevel synthesis compilers assume fixed and known memory latencies thus the technique presented...
A high accuracy experimental platform for Ultra Wide Band (UWB) PN radar performance evaluation has been created. This PN radar platform could be used for the applications such as unmanned-aerial-vehicle anti-collision and short-range distance measurement etc [3]. It includes compact size X-band radar transceiver, baseband signal processing in FPGA, high speed analog to digital converter (ADC), and...
IEEE1588 is a Precise Time Protocol (PTP), which is of potentially wide application in control and measurement networks. Stamping PTP messages accurately in physical layer taking advantage of hardware circuits, it is one of important key technologies to achieve the object of high precision time synchronization of IEEE1588. This paper analyzes the content of IEEE1588 standard in detail, and proposes...
Time to digital converter (TDC) with high resolution is in great demand at present. Transmission delay and its application in a Time to digital technology are studied in this paper. A TDC prototype, mainly contains buffers, delay line and coincidence detection circuit, is designed by this technology. The prototype has a resolution better than 250 ps and a digital range better than 5 ns. The quantization...
in order to achieve the reliable decoding when the real-time video compression bit streams are transmitted in radio channel, the effective channel code method is given. It is based on the Turbo product codes with AHA4501. The performance of its delay time and error correction is evaluated. The selection of block size, the iteration number and frame sync header and is described. And the method has...
Multi-port controller means the share of the memory source, which is mostly applied on occasions for need real time process. This paper firstly introduces the principle of the SDRAM, then a multi-port SDRAM controller based on FPGA is presented, which is apt to the real time image acquisition system. The details from overall concept to sub-modules are focused. This controller has wide scope of application...
We present an embedded jitter measurement system for on-chip diagnostics of serial high-speed interfaces. A Virtex-5 FPGA uses a 3Gbit reference signal to retrieve timing jitter distributions from a system under test (SUT). Using a recently developed fitting method, the total jitter of the system is determined, which allows for judging the quality of transmission lines, PLLs or transceiver structures...
This study design a high precision active radar calibrator (ARC) with programmable echo points which served as control points for both geometric and radiometric calibrations or other applications. The echo delay and Doppler shift of ARC system are fully digitally controlled. Specification and performance of the digital ARC were tested on C-band ERS-2 SAR image. From the experimental results, the FPGA...
The recent trend of reconfigurable hardware and convergence of hardware platform in embedded system have enhanced the application of FPGAs. Although the capability and performance of FPGA have advanced, the testing of FPGAs both online and off-line (manufacturer oriented testing) poses a major challenge. Importance of delay testing has grown especially for high-speed circuits. Even presence of small...
In the design of network-based control systems, network delays and bandwidth variations must be carefully taken into account. In order for the performance of these systems to be optimized, it is necessary to minimize loop delay, and to make it as predictable as possible. In this work, an FPGA implementation is proposed to improve predictability, while at the same time reducing loop delay, in a control...
This article presents the design of RecoNoC: a compact, highly flexible FPGA-based network-on-chip (NoC), that can be easily adapted for various experiments. In this work, we enhanced this NoC with dynamically reconfigurable shortcuts. These can be used to alter the NoC's topology to adapt to the system's communication needs. The design has been implemented and tested on a Xilinx Virtex-2 Pro FPGA,...
The dense routing channels of long global interconnects in today's high performance Field Programmable Gate Arrays (FPGAs), as principle counterpart for ASICs, is a dominant factor in continuous increase in the delay, power, and also the chip area. Using the three dimensional (3D) technology is an essential and also attractive technique to solve these problems. However, the limitation on the number...
In this article, a new methodology for mapping applications onto matrix-based nanocomputer architectures is proposed. It takes into account the structural characteristics and connectivity restrictions of cell matrices and can be used (i) for the partitioning and mapping of applications, (ii) for the generation of alternative mapping configurations with required area, power and delay characteristics...
Cryptographic devices are vulnerable to Differential Power Attacks (DPA). To resist these attacks, the Wave Dynamic Differential Logic (WDDL) has been proposed. However, the limitation of this technique is that it requires balanced routing of the dual rail interconnect between gates, to obtain equal propagation delays and power consumption on differential signals. This paper addresses the problem...
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