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Sub-threshold circuit design has become a popular approach for building energy efficient digital circuits. The main drawbacks are performance degradation due to the exponentially reduced driving current, and the effect of increased sensitivity to process variation. To obtain energy savings while reducing performance degradation, we propose the design of a robust sub-threshold library and post-silicon...
WiMAX (Worldwide Inter-operability for Microwave Access) is an emerging wireless technology standard, which enables high-speed packet data access. To anticipate future demands of WiMAX technology, we propose an all-digital phase-locked loop (ADPLL) based frequency synthesizer for the WiMAX RF transceiver. The developed ADPLL targets frequencies from 2.3–2.7 GHz and from 3.3–3.8 GHz for low band and...
Wireless power transfer technique can be used in many applications nowadays. The main limitation of this wireless power transfer system is in their interface circuitry. In this paper, a highly efficient active rectifier is proposed. By adopting the high speed comparator and, proposed rectifier solved the turn on and off delay of power transistor problem of conventional rectifier and shows high power...
In this talk, key design considerations in deep-volt are summarized with emphasis on the difference between normal voltage design and ultra-low voltage design.
In this paper, we present a new seizure detection algorithm and the associated CMOS circuitry implementation. The proposed low-power seizure detector is a good candidate for an implantable epilepsy prosthesis. The device is designed for patient-specific seizure detection with a one variable parameter. The parameter value is extracted from a single seizure that is subsequently excluded from the validation...
In this article, the main design tradeoffs in design of ultra-low-power (ULP) and robust digital systems will be discussed. Here, the goal is to explore the main tradeoffs among design parameters such as device sizes and supply voltage, and system parameters such as robustness and energy dissipation. This study provides the necessary basis for design optimization and comparing the conventional CMOS...
A study of an eight-transistor (8-T) SRAM cell and its implementation in carbon nanotube FET (CNTFET) technology is presented. CNTFETs have shown great potential as post-silicon CMOS technology due to their superior transport properties, improved current density and excellent robustness to process, voltage and temperature variations. HSPICE simulations demonstrate great advantages for this cell design...
We propose a hybrid spin-charge fabric with computation in spin domain and communication in charge domain. In nanofabrics based on non-equilibrium physical phenomenon like interference of spin waves, switching times are lower than the thermal relaxation times leading to fast multi-value logic at high fan-in without the exponential performance degradation noticeable in CMOS. While computation is much...
Reducing the supply voltage is by far the most widely used low-power technique, as reducing dynamic power quadratically and leakage power linearly, while sacrificing on performances. A similar but less explored route is to reduce and/or limit currents (instead of reducing voltages), e.g., through transistor sizing. This paper details a comparison of a reverse-sized CMOS scheme (which reduces currents),...
In literature delay locked loop (DLL) architecture is used for synchronizing the on-chip serial interconnect transceivers instead of phase locked loops (PLL) due to increased stability and low jitter. In this paper, the design and implementation of a Mixed-Delay Locked Loop (DLL) for on-chip serial transceiver is carried out with a modified architecture, which takes less number of clock cycle for...
Switched capacitor circuits have become a popular method for implementing mixed signal blocks in standard CMOS technologies. Non-Overlapping Clock (NOC) generator is a key building block of switched capacitor circuits. Standard NOC circuits use simple inverters to realize delays. For high to moderate frequencies, the number of inverters required is nominal. But for low frequency applications like...
In this paper a tunable CMOS ring VCO (Voltage Controlled oscillator) is presented based on five-stage differential structure in a wide frequency range. The proposed VCO circuit is designed in CSMC 0.5µm CMOS process and simulated with Cadence Spectre. The power supply voltage is 5V. Simulation results indicate that the frequency is tuned from 10.85MHz to 148MHz when the control voltage varies from...
In this paper we propose a phase-sensitive pixel concept based on an avalanche photodiode (APD) with a charge sensitive amplifier (CSA) readout circuit, and its implementation in a standard CMOS technology. We exploit the principle of APD gain modulation to realize the functions of optical sensing and demodulation of light signals in one component, which can be exploited in several application domains,...
In nano-scale digital CMOS ICs, technology parameter variation limits the usefulness of traditional corner-based timing simulation in favor of statistical simulation. Yet, logic level delay modeling featuring technology variation aware timing is an open challenge. We present a new semi-empirical delay model of digital CMOS cells, accounting for input slope and technology parameters, featuring Spice-level...
VLSI design techniques are the key to re-engineering the digital gadgets of any kind which are needed to be operated with lower power to ensure a longer backup time. Power reduction in Arithmetic Logic Unit (ALU) is needed for this requirement. Multipliers and adders are the most important structures which use a larger fraction of power in such arithmetic units. This paper analyses the use of an ancient...
In Flash ADC designs, the speed of thermometer code to binary code encoder often becomes the bottleneck in achieving ultra high speed. This necessitates new design for encoder which can operate accurately at multi Giga hertz range. In this paper, a unique encoder design technique is presented which exploits the signal pattern in thermometer code and generates corresponding binary bits using lower...
Due to relatively constant and low resistive path between input and output, Transmission gate (TG) logic offers less delay compared to other logic styles without threshold drop while keeping low transistor count. Apart from transition time, the load impedances and initial conditions on internal node capacitances, the critical delay of TG logic depends on chain-length (n) of the circuit and shows quadratic...
The novel topology of the CMOS ring oscillator array is proposed, where the array elements are braided. Compared with the conventional topology of the CMOS ring oscillator array, the proposed oscillator array possesses the nature of the tight and bi-directional connections, and will has the possibility of the phase noise performance improvement. To verify the performance improvement of the proposed...
This paper reports on a voltage controlled ring oscillator fabricated in a 130nm CMOS technology. The oscillator was obtained cascading three delay cells. The schematic of the single delay cell was kept as simple as possible by avoiding the use of cross-coupled pairs. The achieved low phase noise makes the presented ring VCO useful for the design of a correlation radar to be used in medicine for short...
Voltage reduction is a very widely used low-power technique (as reducing dynamic power quadratically, and leakage power linearly) which does sacrifice performance. An alternate technique, which is much less explored/investigated, is to rely on currents instead. The paper presents a thorough but still preliminary comparison of a recently introduced CMOS design technique which limits/reduces currents,...
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