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We propose a performance verification technique for cyber-physical systems that consist of multiple control loops implemented on a distributed architecture. The architectures we consider are fairly generic and arise in domains such as automotive and industrial automation; they are multiple processors or electronic control units (ECUs) communicating over buses like FlexRay and CAN. Current practice...
We consider the control of distributed systems composed of subsystems communicating asynchronously; the aim is to build local controllers that restrict the behavior of a distributed system in order to satisfy a global state avoidance property. We model our distributed systems as communicating finite state machines with reliable unbounded FIFO queues between subsystems. Local controllers can only observe...
In this paper, we described the Queuing delay in our own MLFFA architecture based on data fusion and analyzed different data fusion filter architectures available in the literature with our new Multi-level Federated Architecture (MLFFA) to improve the filtration of each signaling sensor for a reference sensor (RS) within its fusion domain. It is done by sending the individual sensor data through multiple...
This paper describes an implementation of multi-layer techniques using the network infrastructure provided by FEDERICA, PASITO and OneLab projects. FEDERICA project provides a network infrastructure, based on virtualization capabilities in both network and computing resources, which creates custom-made virtual environments. PASITO is a layer-2 network that connects universities and research centers...
This paper presents a high speed architecture for composite field arithmetic based SubBytes transformation (S-box) used in Advanced Encryption Standard (AES) encryption. The proposed architecture is derived by extending the pre-computation technique suggested recently by Liu and Parhi to a recently proposed architecture of AES S-box due to Rashmi, Mohan and Anami. The proposed design of S-box is shown...
In this paper we present an adaptation of a congestion driven placement technique to a Mesh based FPGA architecture containing a local interconnect connections. This techniques aims at spreading out congestion by considering white spaces and avoiding signals bounding boxes overlap. As shown in the experimentation section this technique reduces required routing channel width efficiently and consequently...
Many protocols and communication standard appear in the Substation Automation System (SAS) world. Advanced communication standards a low the exchange of peer to peer information between primary devices in order to accomplish distributed automation application inside SAS. Evaluating the conformity of primary devices towards security and SAS architectures towards required specifications is a non trivial...
There are many studies dealt with handoff management in mobile communication systems and some of these studies presented handoff schemes to manage this important process in cellular network. All previous schemes used relative signal strength (RSS) measurements. In this work, a new proposed handoff scheme had been presented depending not only on the RSS measurements but also used the threshold distance...
In this paper, we have proposed a new SRAM cell architecture which consists of an asymmetric inverter pair to reduce the power consumption. In this work, we reduced the power and delay during write operation by a significant amount. However the area will be increased slightly. The average power consumption in SRAM cell is reduced by about 65.50% during a write operation and reduction in write delay...
Coordinated multi-point (CoMP) transmission and reception is a network multiple-input multiple- output (MIMO) technology considered in 3GPP LTE- Advanced systems. In order to improve reliability and capacity of the services for the user equipments (UEs) at the cell edges, CoMP utilizes cooperation among neighboring enhanced node Bs (eNBs). Accordingly, backhaul delay for sharing control signals among...
FPGA architects typically use experimental techniques to design new architectures. These techniques are time consuming, thus limiting the number of the architectures that can be investigated. Some previous works use analytical models to significantly accelerate the design of a new architecture. To properly capitalize on the benefits of the analytical models, the designers need to have an understanding...
Computer networks serve billions of users all over the world. Research in this field could be performed by building test beds in labs. However, this approach is very expensive, inflexible and hard to reconfigure. It is also difficult and sometimes impossible to replicate some scenarios with test beds. Network simulation on the other hand overcomes all these difficulties. Network simulation can be...
The state of the resources at a destination in Grid computing over OBS architecture (GoOBS) may change between a task's selection of a destination and its arrival at the destination. These changes in the availability of the resources requested at the destination may lead to blocking of tasks, and thus increase the resource blocking rate. In this paper, we investigate the resource scheduling problem...
We introduce a new logic style called Pseudo-Static Current Mode Logic (PSCML), which aims to alleviate the power consumption and delay overhead concerns that have thwarted the wide-spread acceptance of a previously proposed Dynamic Current Mode Logic (DyCML) style. Different from DyCML, the proposed new logic style may be viewed by its environment as static, hence any PSCML-based gate/module can...
Given the increasing complexity of current embedded systems, hardware design is being pushed to a higher level of abstraction, with High-Level Synthesis tools enabling hardware synthesis from untimed C++. Still, HLS technology does not provide a clear methodology to derive both hardware and software implementations from a single high-level code. This paper describes the design, implementation and...
Energy-efficient fast adders are needed in the design of battery-powered portable devices. Although many fast adder architectures exist, most of them require transistor-level optimizations that prevent their synthesis in a standard-cell flow. This paper presents two energy-efficient Add-One Carry-Select Adders (A1CSA and A1CSAH) suited for standard-cells synthesis. Synthesis results showed that the...
A low power Delay Locked Loop based Clock and Data Recovery circuit has been designed in this paper. A standby filter is a novel feature in this design. Level tracking technique is used for data recovery. The circuit is designed using Verilog HDL. The layout of the circuit is generated and verified using Cadence SoC Encounter. Total die area and total dynamic power dissipation of the circuit is 0...
The paper describes an enhanced logical effort model (LEM) to consider UDSM effects in delay calculations. As complex and large fan-in cells can result in an optimized realization of designs, the enhanced LEM is used to determine the stack length criteria as a limit of the cell complexity allowed for technology partitioning in a library-free logic synthesis paradigm. The enhanced LEM has shown to...
This paper presents a new high-speed FPGA implementation of a pipelined adaptive multilayer perceptron (MLP). The proposed approach is a fully parallel architecture based on the delayed backpropagation algorithm, which permits to reduce the critical path and consequently increases the operating frequency. Results obtained with nonlinear function approximation show that this pipelined parallel architecture...
An efficient design of the reverse converter forthe three-moduli set {2n, 2n+1-1, 2n-1} is presented in thispaper. The reverse converter is structured by an adderbased on New Chinese Remainder Theorem II (NewCRT-II) conversion such that it can improve thehardware cost. The proposed conversion design iscompared with the existing works based on the standardCell TSMC 0.18µm CMOS technology. Under the...
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