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Circuit designing using CMOS logic is the promising field for VLSI engineers, but with demand of small and portable devices, new techniques for low power are emerging. This paper proposed four different 10-T subtraction logic using Gate Diffusion Index (a new technique for low power design). Simulation results are performed using 180nm technology using Cadence Virtuoso. Complete verification for performance...
Reversible logic is an emerging technique of upcoming future technologies. Low heat dissipation and energy recycle principle are encouraging its demand for low power daily usage portable devices. In this paper, two reversible gates have been proposed, named as R-I gate and R-II gate, for realizing reversible combinational logic circuits. The proposed two gates can be used for realisation of basic...
In this paper, we present a performance comparison of Binary Coded Decimal (BCD) Adders on Field Programmable Gate Logic (FPGA) for functional and behavioural verification. Although it does not prove that the circuit is reversible, implementation on FPGA serves as a platform for functional verification of circuits. BCD adders are one such circuit which has gain wide research emphasis where BCD adders...
Reversible logic is an emerging technique of upcoming future technologies. Low heat dissipation and energy recycle principle are encouraging its demand for low power daily usage portable devices. In this paper, two reversible gates have been proposed, named as R-I gate and R-II gate, for realizing reversible combinational logic circuits. The proposed two gates can be used for realisation of basic...
The power consumption is a major concern for emerging applications like mobile phones, digital cameras, pace makers and multimedia processors. The power consumption can decreases by number of ways. The multiple supply voltage design is a dominant technique for the reduction of power consumption in System on Chips/Cores. The System on Chips /Cores uses level shifters and the level shifter will become...
Wireless Mesh Network (WMN) is a promising wireless technology for several emerging and commercially interesting applications. It is a multi-hop wireless access network where nodes can act both as a host as well as a router. The proposed work focuses on architecture of hybrid mesh network such that gateway routers are used for accessing the internal or external network. The mesh router has been divided...
Carbon Nano-Tube Field Effect Transistors (CNFETs) are considered to be a promising candidate beyond the conventional CMOSFET. It is due to their higher current drive capability, ballistic transport, lesser power delay product and better thermal stability. CNFETs specific parameters, such as number of tubes, pitch (spacing between the tubes) and the diameter of CNTs determine current driving capability,...
The most fundamental computational process encountered in digital system is binary addition, to accomplish this process binary adders are used, half adder and full adders are most often used to carry out binary addition. This paper presents a comparative analysis of design of 1bit full adder using conventional techniques and new techniques, the design and simulation of 1-bit full adder is performed...
Recent studies indicate that a significant number of very large delay faults that increase circuit path delays several fold, remain difficult to detect and are only discovered by very carefully crafted and comprehensive two-pattern tests, e.g. cell aware tests. A likely source of such large delays in CMOS is stuck-open faults. These can sometimes still allow the circuit to reach the correct logic...
Carry select adder is fastest adder but it required more area and power. The modern VLSI design systems are small in size and less power consumption so the modification is need in the carry select adder to achieve the reduced area and less power consumption. Two proposed works are introduced in thispaper. First method include the reduction of area and power in Carry select adder by modifying the EX-OR...
Several localization techniques have been proposed to identify the exact location of sensor nodes. Localization is important for computation of many applications such as routing in wireless sensor network. Energy preservation is a challenge in wireless sensor network and many algorithms have already been proposed. The localized node lifetime is maximized by using energy-efficient routing, use of minimum...
The Ex-OR and Ex-NOR gates are the basic building blocks of various digital system applications like adder, comparator, and parity generator/checker and encryption processor. This paper proposes a full swing pass transistor based Ex-OR/Ex-NOR gate which gives better driving capability, less propagation delay and low power dissipation as compared to the existing Ex-ORlEx-NOR circuits, and by modifying...
This paper presents a compact realization of quantum n-to-2n decoder circuit, where n is the number of input bits. The proposed design of the quantum n-to-2n decoder circuit shows that it is composed of the quantum 2-to-4 decoder circuit. We present a quantum 2-to-4 decoder circuit using quantum Peres gate and CNOT quantum gates. Finally, we show an algorithm to construct a compact n-to-2n quantum...
This paper proposes a Low-Power, Energy Efficient 4bit Binary Coded Decimal (BCD) adder design where the conventional 4-bit BCD adder has been modified with the Clock Gated Power Gating Technique. Moreover, the concept of DVT (Dual-vth) scheme has been introduced while designing the full adder blocks to reduce the Leakage Power, as well as, to maintain the overall performance of the entire circuit...
High speed, small-size and low-power consuming devices and systems is the considerable solution for next generation technological solution. The search for new principle of operation of the small-size, high speed and low-power device is becoming more and more important. Hear we studied two dimensional SOI and SON Inverter in nano scale, as well as Power dissipation and Delay is being calculated. We...
Timing Optimization is one of the most important objectives of the designer in the Modern VLSI world. Memory elements play a vital role on Digital World. The basic memory elements of designer considerations are Latch and flip flop. In this paper, we analyze the design of Single-bit Flipflop (SBFF) and made performance comparison over the Multi-bit Flip-flop (MBFF). For improving Flip flop performance...
Continued scaling of bulk CMOS technology is facing formidable challenges. As an alternative, FinFETs offer a promising solution for the 22nm technology node and beyond though they still suffer from process, voltage, and temperature (PVT) variations. Thus, in order to analyze the delay of FinFET logic circuits, statistical static timing analysis (SSTA) is more suitable than traditional static timing...
As supply voltage is reduced, a power constrained test clock can be sped up in spite of the increased delay of the circuit. However, a large reduction in voltage makes the operation structurally constrained, requiring the clock to slow down. We determine an optimum supply voltage that allows fastest clock speed for a given power limit. Examples show that the test time can be reduced by as much as...
This paper demonstrates the reversible logic synthesis for the n-to-2n decoder, where n is the number of data bits. The circuits are designed using only reversible fault tolerant Fredkin and Feynman double gates. Thus, the entire scheme inherently becomes fault tolerant. Algorithm for designing the generalized decoder has been presented. In addition, several lower bounds on the number of constant...
This paper demonstrates reversible logic synthesis for (n, k) unidirectional logarithmic barrel shifters, where n is the number of data bits and k=log2n. The circuits are designed using only reversible fault tolerant Fredkin gates. Thus, the entire scheme inherently becomes fault tolerant. Several lower bounds on the numbers of garbage outputs and constant inputs have been proposed. The comparative...
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