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We present an approach to realize wideband and low-loss antennas and antenna arrays on chip. The radiators are loaded with an artificial dielectric superstrate to improve the bandwidth and the overall efficiency. An example of design is proposed, consisting of an array of connected-dipole elements operating in a frequency band around 300 GHz. The antenna elements are located in the close proximity...
This paper describes electrical characteristics of bumpless and dual-damascene TSV interconnects for three-dimensional integration (3DI) using Wafer-on-Wafer (WOW) technology. Process optimization counter to integration issues of TSV formation process is demonstrated using test vehicle fabricated with 300-mm wafer and characterized by chain resistance and leakage current in the wafer level.
Most terahertz metasurfaces utilise metallic resonators for various functions ranging from filtering, polarisation conversion, modulation, perfect absorption, to beamforming. Here we show that silicon can replace metals to build resonators for similar functions with superior performance. In one case, moderately doped silicon is shown to support terahertz surface plasmon polaritons. Resonant cavities...
In this paper, we reported the TSV Via last from backside (BVL) etch integration challenges and Etch process optimization. We demonstrated the 10×40 um TSV via last (BVL) etch integration and discussed on various TSV profile. The fabrication of BVL was also reported including temporary bonding, wafer planarization, TSV liner deposition and Via bottom 1st and 2nd etch characterization.
In Micro and Nano Technology, the downscaling of semiconductor devices requires the usage of alternative semiconductor material for SiO2 as the gate dielectric. It requires new structure so that the higher current can be achieved. In view of this, in the present paper a structure of double-gate MOSFET with HfO2 has been analysed. This paper includes an effect of threshold voltage on symmetric double-gate...
With the semiconductor development, more and more different devices need be integrated to achieve faster and more functionalities. Micro-bump is an important connection from chip to chip, chip to wafer and chip to substrate. We evaluated micro-bump barrier layer Ti thicknesses (400Å, 1KÅ and 2KÅ) effect on shear strength and bump chain resistance in this study.
Chemical Mechanical Polishing (CMP) on thinned bonded wafer is one of the key challenges in the entire via-last TSV process flow. This paper addresses the issue of oxide loss and barrier metal residue during CMP process. The impact of pre-CMP thermal budget on (i) CMP polishing rate, (ii) uniformity and (iii) selectivity to the underlying dielectric on bonded wafers is investigated. We further looked...
The surface treatment of low-k dielectric layers by exposure to atomic oxygen is presented as an alternative to plasma based treatments prior to barrier layer formation. High carbon content porous low-k dielectric films were subjected to increasing exposures of atomic oxygen and x-ray photoelectron spectroscopy (XPS) studies reveal both the depletion of carbon and the addition of oxygen at the surface...
Scaling down of the semiconductor devices from micro to Nano scale has now become the trend for the electronics industry and it is the only hope that can ensure lesser power consumption and also reliability. Ultra thin MOSFET's, Double Gate MOSFET's, FINFET and now the latest development is the Nanowire FET. The nanowire FET is a revolutionary device as the gate is all around the channel which provides...
The effects of thermal annealing on the interface reactions and bonding structures of CeO2/La2O3 stacked dielectrics are investigated by x-ray photoelectron spectroscopy (XPS) measurements. We found that the thermal treatment can lead to significant interface oxidation and silicate formation both in the bulk and at the interface. Sample with 600 °C annealing exhibits some better interface properties...
We characterize free carrier effects in silicon waveguides due to electronic non-idealities such as dielectric fixed charges and interface states, independently considering SiO2, SiNx and Al2O3 cladding layers. These effects are shown to impact both the passive and active properties of silicon waveguides.
Numerous techniques have been used to improve the breakdown voltage (VBR) capability of high voltage devices with the aim of getting closer to the breakdown voltage of a plane parallel junction. In this work, a peripheral protection for a 3 kV SiC bipolar diode is presented. This protection concept is based on a large and deep trench filled by an insulating material. This trench is called Deep Trench...
This work investigates the influence of discrete dopant positions and lead geometry on the contact resistance in ultrascaled nanowire field effect transistors (NWFET). We use Green’s function approach self-consistently coupled with Poissons equation to show that impurity levels play an important role in current transmission from the highly doped regions to the channel of realistic NWFETs. We find...
We report mobility simulations for long channel Si and InGaAs MOSFETs as a function of the semiconductor film thickness and inversion charge. Calculations account for numerous relevant scattering mechanisms and surface roughness is described by the recently developed non-linear model [1]. Reasonable agreement with available experiments is obtained employing the measured surface roughness r.m.s. value...
This paper presents promising current-voltage characteristics of semiconductor-insulator-graphene tunnel diodes as the hot-electron injection unit in graphene base transistors (GBTs). We propose that by using a bilayer tunnel barrier one can effectively suppress the defect mediated carrier transport while enhancing the hot-electron emission through Fowler-Nordheim tunneling (FNT) and step tunneling...
We study the efficiency of several types of all-dielectric light-trapping and antireflective coatings for the enhancement of photovoltaic absorption in thin-film silicon solar cells. We compare the photovoltaic absorption enhancement offered by a square array of nanovoids in the dielectric covering of the cell with that granted by a flat blooming layer, and a densely packed array of dielectric nanospheres.
We propose the design of a dielectric flat lens for visible wavelengths, capable of efficiently focus the incident field at a given distance. Our approach relies on the recently proposed exploitation of high-index dielectric resonators with spectrally overlapping electric and magnetic dipole resonances of equal strength. This allows the design of “metasurfaces” characterized by a nearly-full transmission...
We present an optical imaging system based on photonic hypercrystal, an artificial optical medium combining the properties of hyperbolic materials and photonic crystals. This system functions as a negative refraction lens with substantially reduced image aberrations.
Dielectric laser accelerators are a compact and scalable alternative to radio frequency accelerators. We present the first demonstration of over 200 MeV/m acceleration and deflection gradients with a silicon structure at 96.3keV electron energy.
The interfacial region between a base matrix and nanoparticles in nanocomposite dielectrics is often referred to as the main cause of good performance of nanocomposites as insulating materials. In the present work we compare electronic structure of the interfacial region in the polyethylene magnesium oxide nanocomposite with the electronic structures of its bulk constituents. The calculations were...
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