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In this paper, the effect of silicon body thickness (TSi) and silicon body width (WSi) variation on DC characteristics in 100 nm gate length silicon-on-insulator (SOI) junctionless (JL) and junction transistors has been investigated by using numerical simulations. The digital figure-of-merits characteristics such as threshold voltage (VTH), on-current, subthreshold voltage, and drain-induced-barrier-lowering...
We theoretically investigated the modulation speed of Si photonic crystal slow light modulators. Optimizing the doping profile of p/n junction reduces the RC time constant and enhances the speed to 40 Gbps.
We evaluated wideband 25 Gbps error-free operation of Si slow light modulators. The fluctuation in extinction ratio was 1 dB over the bandwidth. Larger group indices produce larger extinction ratios and lower bit error rates.
We fabricated Si QPSK and PAM modulators with photonic crystal slow light waveguides and interleaved p/n junction, both of which have footprints less than 1 mm2. 30–35 Gbps operation were observed in 300–450 μm devices.
We observed the avalanche photodiode operation through defect levels at telecom band in Si photonic crystal slow light modulator. Maximum responsivity was 0.71 A/W with 350 avalanche gain. The eye opened at 20 Gbps.
We report analysis of the photo-induced minority carrier effective lifetime (τeff) in p+n junction formed on the top surfaces of n-type silicon substrates by ion implantation of boron and phosphorus atoms at top and bottom surfaces followed by activation by microwave heating. The values of τeff were lower than 1×10−5 s in the reverse bias condition when continuous wave 635 nm light was illuminated...
Reducing the thickness of crystalline Si wafers to be processed into solar cells yields several significant benefits: PV module manufacturing cost can be reduced and the required diffusion length of minority carriers is smaller. The latter in turn enables a higher efficiency potential and a larger spread of Si materials to be employed for rear junction solar cell concepts which are advantageous for...
This paper presents an extendible beyond 20% efficiency cost-efficient roadmap for bifacial solar cell, which is suitable to both p-type and n-type substrate. The roadmap is based on boron & phosphorus implantation and screen print technology. We experimentally demonstrate here bifacial cells using industrial p-type c-Si substrate with front side efficiency of 20% and rear side efficiency of 16–16...
A “four-wire” configuration thin-film silicon solar cell design is proposed. Front and middle TCO layers are optimized in order to be used, together with a Bragg reflector, to increase the useful current in the top cell (by about 1 mA/cm2 according to initial calculations) and hence the total photocurrent. Preliminary results from both experiments and numerical simulations are presented, showing the...
Tandem solar cells using different bandgap materials provide higher energy conversion efficiency than single junction cells. However, the need for current matching and lattice matching often restricts the material selection for multi-junction solar cells. To overcome these challenges, we report AlGaAs/Si dual-junction tandem solar cells fabricated by a combined epitaxial lift-off (ELO) and print-transfer...
We have achieved the first monolithically integrated triple-junction InGaP/GaAsP/SiGe solar cell on Si substrate, achieving an adjusted efficiency of 20% AM0 1-sun. The practical achievable maximum AM0 efficiency for the optimal cell near this lattice constant is 39%. The combination of this high efficiency with the ability to process such cells on larger area lower-cost silicon substrates motivates...
In this paper we present theoretical analysis for upper efficiency limit of a novel 2 terminal dual junction stepcell. Results show that step cell design relaxes bandgap requirements for efficient tandem cell. While conventional tandem cell with optimized bandgap combination (1.64 / 0.96 eV) has the highest efficiency (45.78 %), the step-cell design provides significant efficiency improvement for...
In this work, the potential of Si1−xGex Quantum Wells (SiGe QW) for future DRAM periphery transistors and more generally for Low Power applications is investigated. It is shown that an increase of Ge content in the channel leads to a significant reduction of threshold voltage and to an increase of long channel mobility. However, an increase of external resistance is observed for Si1−xGex Quantum Well...
The ESD robustness of planar Si and Ge diodes on Silicon-on-Insulator (SOI) optical interposer is studied by using TLP and vfTLP system. Although Ge diodes show a lower failure current, a superior clamping capability with a resistance lowering behavior, which is attributed to the intrinsic material properties of Ge, makes Ge diodes possess a promising potential for ESD protections.
We investigated the electrical properties of highly-doped n-Si/n-Si and p-Si/p-Si junctions fabricated by using the surface activated bonding. Heights of potential barrier formed at the respective bonding interface were estimated by measuring dependence of their current-voltage characteristics on the ambient temperature. The heights of barrier were found to be varied due to annealing often the bonding...
Due to the exceptional electrical and optical properties of graphene, public interest has grown rapidly since the material was exfoliated onto SiO2 in 2004 [1–3]. Other two dimensional (2D) crystal materials such as MoS2, hBN, and WSe2, individually or in combination with graphene, also have shown intriguing properties. One of the interesting applications is using the 2D heterojunction as a photodetector...
We have demonstrated high performance operation of planar-type tunnel field-effect transistors (TFETs) using Ge/ III–V materials. Tensile strain in Si channels combined with the Ge source can enhance the tunneling current because of the reduced effective bandgap. The fabricated Ge/sSOI (1.1 %) TFETs show high Ion/Ioff ratio over 107 and steep minimum subthreshold slope (SS) of 28 mV/dec. It is found...
In the overwhelming majority of cases, current-voltage characteristics of metal-based contacts on semiconductors are non-linear around 0V even for degenerate interfacial doping levels. Any contact resistivity specification is therefore meaningless without the knowledge of the effective bias across the contact. For the first time, the efficiency of a dielectric insertion for contact resistance reduction...
In a VNWA Schottky rectifier, Vbr can be raised and/or Rs,sp lowered progressively by increasing S/R. This can be interpreted in several ways: the performance of this rectifier can be improved at the cost of device area; this rectifier offers an additional degree of flexibility in terms of the device area in device design; the structure of this rectifier allows tailoring of Vbr and Rs,sp using a geometry...
High-efficiency tunnel oxide junction cells are based on the Metal-Insulator-Semiconductor concept, which combines a tunnel oxide junction with doped a-Si thin film emitter layers on n-type CZ silicon wafers. The cells are bifacial by design and allow for almost equal power generation from the front and from the back. Packaged inside a module with transparent front and backside allows for light capture...
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