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This paper presents a monolithic approach for the integration of silicon nanowires (Si NWs) with microelectromechanical systems (MEMS). The process is demonstrated for the case of co-fabrication of Si NWs with a 10-µm-thick MEMS on the same silicon-on-insulator (SOI) wafer. MEMS is designed in the form of a characterization platform with an electrostatic actuator and a mechanical amplifier spanned...
In this article, we present a camouflage sheet consisting of nanophotonic structures that can manage thermal signature of objects. Photonic structures that can absorb a wide range of mid-infrared wavelengths were transferred onto flexible substrates to cover objects and absorb their infrared radiations. Transmission and reflection of surface can be reduced by silicon nanowires in the desired region...
In this work we present a simulation study of Si80Ge20 and Silicon vertically stacked lateral nanowires transistors (NWTs) with potential application at 5nm CMOS technology node. Our simulation approach is based on careful selection of simulations techniques in order to capture the complexity of such ultra-scaled devices. We have used ensemble Monte Carlo (MC) simulations to accurately predict the...
We studied the current-voltage characteristics of percolating networks of silicon nanowires (nanonets), operated in transistor mode, with back-gate biasing. These devices featured P-type field-effect characteristics suitable for future use as sensors. It was found that a Lambert W function-based compact model could be used for parameter extraction of electrical parameters such as effective low field...
A model system of three-dimensional (3D) Si nanowire (SiNW) Metal-Insulator-Semiconductor (MIS) capacitor arrays with vertical Si nanowires of diameter 430 nm and height 1.35 and 2.5 µm respectively has been fabricated and studied. The gate dielectric was a 6 nm thick thermally grown SiO2 layer and the gate metal was Al. The SiNWs were formed by using photolithography with an I-line stepper and reactive...
We developed a Multi-Subband Ensemble Monte Carlo simulator for non-planar devices, taking into account two-dimensional quantum confinement. It couples self-consistently the solution of the 3D Poisson equation, the 2D Schrödinger equation, and the 1D Boltzmann transport equation with the Ensemble Monte Carlo method. This simulator was employed to study MOS devices based on ultra-scaled Gate-All-Around...
This paper reports on the first integration of silicon nanonet into long channel field effect transistors using standard optical microelectronic methods. The electrical characteristics of these devices constituted by randomly oriented silicon nanowires are also studied. Compatible integration on the back-end of CMOS readout and promising electrical performances open new opportunities for sensing applications.
Transition from planar MOSFETs to FinFETs enabled scaling beyond 28nm node. At 5nm/3nm design rules, a transition from FinFETs to nanowires has to be evaluated. We explore with rigorous NEGF (Non-Equilibrium Green's Functions) and sub-band Boltzmann transport models the impact of nanowire shape and SiGe/Si cladding layers on its performance and variability. Outside of the nanowire channel, a “bottleneck”...
Energy autonomy keeps being one of the most desired enabling functionalities in the context of off-grid applications, such as continuous monitoring scenarios and distributed intelligence paradigms (Internet of Things, Trillion Sensors). SiNERGY, a European project (GA n° 604169) coordinated by IMB-CNM (CSIC) has focused on silicon and silicon friendly materials and technologies to explore energy harvesting...
This paper reports on the enhanced piezoresistive effect in p-type <110> silicon nanowires, fabricated using a top down approach. The silicon nanowire width is varied from 100 to 500nm with thickness of 200 nm and length of 9μm. It is found that the piezoresistive effect increases when the nanowire width is reduced below 350 nm. Compared with micrometre sized piezoresistors, silicon nanowires...
The simulation and experiment of nano/micro electron field emitters were investigated in this paper. The results indicated that the space–charge effect due to the emitted electrons is important in determining the field-emission current from a nano-emitter because of the shielding effect from the charge particles. Besides, from our FE model results, scaling the emitter radius and gate aperture of FE...
Gold (Au) nanoelectrode ensembles (NEEs) were investigated after the synthesis of silicon nanowires using the metal assisted chemical etching technique. Structural and non-destructive optical characterization of silicon nanowires are carried out to determine its morphology and crystallinity. The cyclic voltammetry technique is used to determine the oxidation-reduction potentials of the sensor at different...
This work presents the analog performance of strained SOI nanowires for the first time. Triple gate MOSFETs made in strained and unstrained SOI material with variable fin widths from quasi-planar transistors to nanowires with aggressively scaled fin width are compared using experimental results in the temperature range of 300K down to 10K. Intrinsic voltage gain, transconductance and output conductance...
Tunnel FETs (TFETs) with steep subthreshold slope have been attracting much attention as building blocks for future low-power integrated circuits and CMOS technology devices. Here we report on recent advances in vertical TFETs using III–V/Si heterojunctions. These heterojunctions, which are formed by direct integration of III–V nanowires (NWs) on Si, are promising tunnel junction for achieving steep...
In this work we investigate the correlation between channel strain and device performance in various n-type Si-NWTs. We establish a correlation between strain, gate length and cross-section dimension of the transistors. For the purpose of this paper we simulate Si NWTs with a <110> channel orientation, four different ellipsoidal channel cross-sections and five gate lengths: 4nm, 6nm, 8nm, 10nm...
This simulation work studies whether band-to-band-tunneling leakage in short-channel germanium FinFETs and nanowires can be mitigated by the band gap widening resulting from quantum confinement. Through a combination of drift-diffusion and coupled Poisson-Schrödinger simulations, two possible solutions are investigated: can the BTBT rate be lowered sufficiently? Secondly, can the tunnel path be cut...
This paper investigates the Total Ionizing Dose (TID) response of nanoscaled Tri-Gate Field-Effect Transistors (FET) made of silicon multiple-gate NanoWire (NW). The NWFET architecture relies on its remarkable electrostatic properties to push "silicons-based technologies much deeper into device scaling than present FinFETs. But as commonly observed when a new device or technology concept is proposed,...
This work investigates quantum ballistic transport in ultra-small junctionless semiconducting nanowire transistors, within the framework of self-consistent Schrodinger-Poisson problem. A sub-band decomposition approach has been taken to make the problem numerically tractable. Finally simulated transport characteristics for small diameter (d≤5 nm) n-Si-channel cylindrical gate-all-around junctionless...
In this work, we have grown GaN nanowires using Plasma assisted Molecular beam epitaxy (PA-MBE) on Si (111) substrate. High resolution X-ray diffraction (HRXRD) characterization and scanning electron microscopy (SEM) studies were carried out to investigate the crystal structure, morphology and uniformity of the grown nanowires. These studies confirm wurtzite crystal structure and uniform growth. The...
In this talk, I will discuss two applications of nonlinear quantum photonics in silicon nanowires: correlated photon pair sources and a single-photon wavelength converter. Correlated photon pairs can be generated in a nonlinear silicon waveguide through the spontaneous four-wave mixing (SFWM) process shown in Fig. 1(a), where two photons from a bright pump laser are annihilated, and a two photons...
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