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An analytical analysis of stress profile in cylindrical nanowires vertically grown on silicon (Si) substrate has been performed. Depending on the lattice-mismatch a tensile stress as high as 1GPa for TiO2 nanowires and a compressive stress of 900MPa for InP nanowires has been obtained. The angular component of stress remains small indicating the nanowires will not be twisted as a result of the substrate-induced...
The effect on the stress profile for more than one nanowire constituting a matrix has been analyzed. There from it has been made evident that substrate as well as process-induced stress, irrespective of its nature, within the basal plane of a single nanowire gets reduced in a cluster of closely packed nanowires.
We demonstrate for the first time that InAlAs/InGaAs QW can be selectively grown on micron-sized InP-OI substrates, obtained by selective epitaxy in empty oxide cavities on Si. The concept, material and optical characterizations are presented, paving the way towards integrated light sources for infrared applications.
We report on the integration by transfer printing of III-V Fabry-Perot cavities on a silicon photonic circuit. We pre-process the III-V coupons on their native substrate, transfer print onto the target SOI, and post-process the printed coupons. We report light coupling into the photonic circuit.
Compressively strained GeSn alloys grown on Ge buffers on Si (001) substrates were fabricated into microdisks and strained using silicon nitride stressors. The strained disks are measured to be tensile by Raman spectroscopy, and demonstrate direct bandgap emission in the 3–5 μm gas sensing window.
We experimentally and theoretically analyze the role of substrate on the optical bound states in the continuum (BICs). We reveal that a high-index substrate could destroy even in-plane symmetry protected BIC due to leakage into the diffraction channels opening in the substrate. We show how two concurrent loss mechanisms scattering due to surface roughness and leakage into substrate contribute to the...
In this paper, we present a study on protective coating techniques for thin film X-TEM sample preparation. The study shows that proper choice of the protective layer before FIB cross section is a crucial step to maintain the film profile and make sure the accuracy of the thickness measurement. Silicon native oxide is used as the target sample. We have investigated PECS metal sputtering followed by...
In this paper, we present one simple die-level backside silicon thinning preparation approach to enable fault localization of vertical trench or highly doped silicon substrate power semiconductor devices. The methodologies are illustrated for understanding and immediate application at any lab environment. Effectiveness of the method is evaluated through qualitative judgement of image resolution clarity...
A back-side grinding CMOS-MEMS process is well established for thinning wafers down to tens of micrometres for use in stacking chips. As a result of the mechanical process, the wafer backside is compressively stressed. In this paper, authors investigate the influence of the backside induced stress in MEMS/CMOS wafers thinned down to 35∼275 μm by means of a micro-Raman technique. We found that the...
In this study, a comparison of the interfacial adhesion strength of Plasma Enhanced Chemical Vapor Deposition (PECVD) silicon nitride (SiN)/Cu and High-Density Plasma Chemical Vapor Deposition (HDP CVD) SiN/Cu was performed using the 4-Point-Bending (4PB) technique. Differences in critical energy release rate value Gc, which is an indicator of the interfacial adhesion strength, were observed. The...
Previous experiments have showed that carbon island films (quantum dots) at silicon can be capable of low-field electron emission. This paper presents new results of experiments on comparative characterization of emitting and non-emitting thin carbon films. Auger spectroscopy, Electron Energy Loss Spectroscopy, Anderson's technique for work function measurement and secondary-emission techniques confirmed...
We fabricated a high performance electron beam for the vacuum electronic devices with carbon nanotube (CNT) cathode. For the vacuum electronic devices application, a structure of cold cathode should be highly adhere on cathode substrate and endure a resistive heating during electron emission. For fabrication of stable electron beam, we optimized the CNT emitters and the triode structure. The structural...
Large-tilt angle (LTA) implantation has been employed in Si manufacturing processes in many applications, such as lightly-doped drain and Halo Implant. The depth profile of implant ions usually consists of only single peak at incident angle of zero degree with respect to the perpendicular of the silicon surface. However, an abnormal dual-peak profile was observed at LTA (>40 degree) for both boron...
Si nanocrystal samples were fabricated by pulsed laser deposition method. Through changing the growth Ar gas pressure, the Si nanocrystal size and density can be controlled. Our works provided a possible way to fabricate Si nanocrystal embedded nonvolatile memory.
We report on a 32-MHz quartz TCXO fully integrated with commercial CMOS electronics and vacuum packaged at wafer level using a low-temperature MEMS-after quartz process. The novel quartz resonator design provides for stress isolation from the CMOS substrate thereby yielding classical AT-cut f/T profiles and low hysteresis which can be compensated to < ± 0.2 ppm over temperature using on-chip third-order...
We report a fabrication method of nanoscale quantum-dot (QD) organic light-emitting diode (OLED) structure suspended on a monolayer hexagonal boron nitride (h-BN) sheet on nano-hole-patterned SiO2/Si substrate. In our proposed OLED, the junction area is defined by a non-lithographically patterned oxide layer on Si substrate. We utilized self-organized gold nanoparticles to create nanoscale etch windows...
We have investigated the mechanisms of oxide breakdown in a graphene/SiO2/Si (GOS) capacitor structure under high-field pulsed voltage drive. Four different configurations are analyzed and compared in terms of bias polarity and substrate conductivity type: inversion or accumulation bias on a GOS structure formed on n-Si or p-Si substrate. Electric field distributions in the GOS structure are analyzed...
This paper reviews our recent work on DNA-based nanofabrication. DNA nanostructures were used as a template to initiate direct pattern transfers to a diverse range of substrates, including oxides, polymers, and self-assembled monolayers. Complex patterns were obtained in many cases with a lateral resolution down to sub-10 nm demonstrated in some cases. These results highlight the potential of DNA...
We report a quantum-dot (QD) organic light-emitting diode (OLED) structure formed on Si substrate scaled down to nanometer dimensions. In our proposed OLED, the junction area is defined by a non-lithographically patterned oxide layer on Si substrate. We utilized gold nanoparticles as oxygen barrier mask during thermal oxidation of Si. Previously, we demonstrated a carrier injection mechanism originating...
Hybrid halide perovskite has made great advances for making new composition of materials, which have wide usage in advanced optoelectronic devices. Here we show amplified spontaneous emission (ASE) in a perovskite nanograting metasurface, defined by the cost effective nanoimprint lithography method which cannot typically be applied to hard, ionic based materials such as perovskite.
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