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A wettability patterned surface has been developed to manipulate nucleation boiling in a micro fluid flow channel. The wettability patterns was fabricated by using hydrophobic dots on hydrophilic surfaces which form non-wetting islands and wetting network. The hydrophobic hexagon dots with a side length of 30μm and pitch distance 60μm are fabricated with Teflon (Teflon AF 400s2-100-1, DuPont) which...
Fan-out wafer level packaging (FOWLP) not only provides simplified supply chain management and lower cost structure, but also enables thinner profile and heterogeneous system integration. FOWLP is becoming increasingly significant and is projected to drive growth in advanced packaging for the foreseeable future. There are many different processing technologies for fabricating FOWLP. One common key...
There are strong needs for flexible and stretchable devices for the seamless integration with soft and curvilinear human skin or irregularly textured clothes. However, the mechanical mismatch between the conventional rigid electronics and the soft human body results in many problems. Since nanoscale materials can provide mechanical and electrical versatility, various nanomaterials have rapidly established...
A novel HD-FO package platform was introduced with a hybrid RDL structure. An HD-FO package with hybrid RDL could enables higher routing density and multi die construction in a planner configuration. The 1-µm and submicron RDL wafers were fabricated at a foundry and then the essential parts of the inorganic RDL were integrated with Amkor's internal organic RDL process making a hybrid structure. Also,...
An aluminum-nitride (AlN) based energy-harvesting MEMS sensor is developed. We aimed at realizing energy-harvesting sensor with functional feature of wide-band response at low-frequency vibration domain, owing to the high-power density of vibration sources energy in a particular low frequency with several Hz deviations. By simplifying and analyzing the vibration module of the sensor structure, a special...
This paper presents a low-cost and high-precision pH sensor using silicon nanowire (SiNW) array. With the help of traditional microfabrication technology, low-cost as well as highly controllable SiNW array was fabricated. After functionalized with APTES solution, SiNW array shows rapid and reliable response to pH value. With excellent linearity and repeatability, accuracy of the sensor can be achieved...
This paper presents the methods of eliminating the plasma-induced Si substrate damage in periphery regions, resulting from high aspect ratio etching process for 3D NAND fabrication. The impact of Si substrate damage is verified by the low and high bias power experiments. The result indicates more Si damage is present with high energy bombardment; therefore, high bias power is recommended to be inhibited...
This paper presents thermal performance characterization of ultra-thin silicon vapor chambers suitable for integration into packages, including possibly interposers. 720±10 pm thick silicon vapor chambers at three different wick porosities have been fabricated using photolithography and deep reactive ion etching (DRIE) to create chambers, followed by inkjet printing and self-assembly to create patterned...
This work introduced a novelty MEMS pyroelectric infrared detector based on LiTaO3 (LT) crystal with high absorptivity amorphous carbon film layer. The LT crystal is thined and polished to 100um thickness and double mentaled for electical connection which will be suspened upon rectangle cave of silicon substrate with mental ring. Amorphous carbon(a-C) could be produced by magnetron sputtering on the...
This paper used an effective annealing process to improve the performance of Parylene C micropore-arrayed membranes fabricated with Parylene C moulding strategy. The results indicated that the annealing treatment at 320°C for 2h in nitrogen sealed the keyholes, which were unavoidably generated in the conventional Parylene C moulding process, because of melting and reflow at high temperature. A chromatic...
We propose a wafer-scale technique for nanostructure formation inside vertically oriented, through-membrane nano-pores. It uses 50 nm monocrystalline silicon pillars as a mold, embedded in a silicon nitride membrane formed in an innovative step. The proposed technique paves the way towards advanced functionalization of parallel oriented nano-pores for actuation, sensing, filtering/trapping purposes.
TSV (Through Silicon Via) is one of advanced semiconductor technologies for miniaturization and improved performance at the system integrated circuits. Recently, more complex module should be required this process to be integrated. There specific module for a mobile wireless communication, called TSV (Through Silicon Via) module is now adapted and imbedded with individual passive devices. In this...
Surface photovoltage (SPV) method was used to evaluate the silicon-sapphire interface potential barrier of silicon on sapphire (SOS) wafers obtained by CVD technique. The method provides monitoring of silicon-sapphire interface quality. Fabrication process parameters which influence on SPV signal were found. Silicon deposition temperature has a great importance on SPV signal. It was found that SPV...
The article examines physical principles, conceptual design and fabrication of integrated pressure transducer manufactured by means of microelectronic technology — MEMS and its optimization questions. Spatial distribution of the intrinsic stress caused by the transducer manufacturing and its current heating by supply current was studied by the method of modulation polarimetry.
Nanometre scale pores, gaps or trenches are of significant interest for a number of applications in nano and microsystems, including biosensors, nanofluidic devices and mechanical resonators. This paper presents the design of two test structure chips for the development of a process capable of the fabrication of controllable nanoscale trenches or gaps. This process uses uses standard microfabrication...
Digital fingerprinting refers to as method that can assign each copy of an intellectual property (IP) a distinct fingerprint. It was introduced for the purpose of protecting legal and honest IP users. The unique fingerprint can be used to identify the IP or a chip that contains the IP. However, existing fingerprinting techniques are not practical due to expensive cost of creating fingerprints and...
Thin film copper membranes on silicon substrates were constructed using micromachining techniques. Membranes were used as flexible ground planes beneath a microstrip transmission line. Actuation of membranes induced phase shift in the transmitted signal. Membranes possessed radial surface corrugations 10 μm deep to increase their flexibility. Membranes were released using a combination of KOH and...
We presented a self-organized, MOS gate-stacking structure of SiO2/Ge-dot/SiO2/Si1−xGex-shell, using thermal oxidation of poly-Si0.85Ge0.15 nanopillars over buffer Si3N4 on the Si substrate, for the fabrication of high performance Ge-dot photo MOSFETs. Low dark current of 3 μA/μm2, Superior high photo responsivity of 1400–710A/W, and short response time of <0.8ns are measured on 90nm Ge-dot photo...
Specifications and fabrication process suitable for a small wafer with the diameter of half-inch, which is used for a minimal fab, is presented. We beveled wafer edge by rapping and polishing in order to clean the edge and to suppress the strong surface tension at the edge. To show the crystallographic orientation of the wafer, we introduced laser marking process. By the processes, we have formed...
In this work we show a baseline fabrication process of interdigitated back contacted IBC c-Si(p) solar cells, which combines conventional diffusion oven stages to define base p+ and emitter n+/n++ regions at the back side, with outstanding front surface passivation using atomic layer deposited Al2O3 films over random pyramids surfaces. Cells include a selective phosphorous n++ emitter in order to...
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