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Zinc oxide (ZnO) thin films were grown on three kinds of substrates (copper, silicon and glass) by the SILAR method. The solution was prepared by using zinc sulphate ZnSO4 and ammonia NH3. And for rinsing, we heated the distilled water at the temperature 80°C. The nature of substrate was found to have effect on the crystal structure, morphology and optical properties of the resultant ZnO thin films...
The aim of this article is to build a comprehensive thermal model of the power IGBT modules in 6 kVA solar inverter. The thermal model is defined in order to predict the junction temperature, using different values of power dissipated. The thermal model is developed by using a new RC model which is implemented in SIMULINK/M. The results of the RC network are comparing with the 3D Finite Element Simulation...
Wide band gap semiconductor devices have a promising future in various power converter applications due to their higher performance characteristics such as high frequency, high voltage and high operating temperature. For power switching applications, wide band gap materials mainly Silicon Carbide (SiC), Gallium Nitride (GaN) and Diamond are attractive. In this paper, the detailed design analysis for...
Many Intel PRC customers worked on low-cost solutions in server platforms. This paper introduced a method to investigate dual strip line performance on high-speed interfaces like DDR and PCIe. Through a practical design on an Intel Haswell-EP server platform in Huawei, we achieved 4-PCB-layer reduction compared to the original board, saving system bill-of-material cost effectively. Pre- and post-layout...
Reported here is an experimental study and mechanical characterization of the annealing process of TSV structures. A major focus of this study is the extent of thermo-mechanical stresses, which form during this processing step. Results of bowing as well as copper protrusion measurements before and after the annealing process are presented as indicators for the stress development during the heating...
Thermal conductivities of different interconnect sections of power MOSFETs were numerically determined using the Stationary Thermal Analysis mode of the ANSYS software. From the numerical solution, the thermal conductivities in the directions of the coordinate axes were calculated from the specified temperature difference on the opposite faces of the simulation box and the thermal flux through these...
Heat generation in integrated circuits has become in few decades one of the most limiting factors for performance improvement in mobile device components, such as cell phones or tablets. In these devices, heat dissipation is limited to a few Watts as state of art cooling systems, such as heat-sinks or fans, do not fit with the dimensional and power consumption constraints. Amongst the solutions proposed...
This paper reports results on FEM modeling in order to calculate stress distribution at the Cu/Si boundary of TSVs after the fabrication process (annealing) using ANSYS software. Residual interfacial shear stress is estimated to be close of 200MPa for a 5μm radius circular copper filled TSVs while Von-Mises simulations give a radial distribution with a maximum above 500MPa around the TSV. All these...
The SnPb solder ball was reflowed on the Cu film in a flow of reducing gas, and the reactive spreading process was in situ recorded by a CCD camera. On the thicker Cu films, it was observed that dewetting did not happen even if the Cu6Sn5 intermetallic compounds spalled into the liquid solder. However, on the thinner Cu films, dewetting would occur when the liquid SnPb solder consumed the underneath...
The sputter-deposited Cu thin film, coated with a thinner gold layer, was prepared into the butterfly pattern with alternating zones beween Cu thin film and Si. The eutectic SnPb solder balls with different sizes were reflowed on the butterfly pattern. As a result, the liquid solder would be selectively retained on the Au/Cu film zones. At the same time, under the energy minimization control, the...
Temporary bonding and release processes are regarded as the critical technologies in 2.5D and 3D IC integration. The process is especially challenging when the device contains high topography structures like copper pillar bumps. This paper presents the results of simulation, bumping process, wafer temporary bonding, thinning and debonding. Through careful consideration and optimization of the above...
Though Silicon Vias(TSVs) are regarded as a key technology to achieve three dimensional(3D) integrated circuit(IC) functionality. Annealing a silicon device with TSVs may cause high stress and cause TSV protrusion because of high Coefficient of Thermal Expansion(CTE) between silicon substrate and TSVs. The TSV wafers could be annealed right after copper plating process, or after chemical mechanical...
Through silicon via is an essential element for three dimension integration. Excessive stress have potential effects on the reliability of the structure. One concern is the peeling problem of SiO2 layer. It was found that it is caused by the electroplated copper during later solder reflow process. We also found that it is possible to ameliorate the peeling problem by increasing the compressive stress...
Through silicon via (TSV) is the critical structure for three dimensional package technology, which provides vertical interconnections between stacking dies and interposers. However, for TSVs, there are still some reliability problems and metal core warming of TSVs is involved in most of the causes. Thus, accurate and efficient thermal modeling methods describing and quantifying metal core warming...
Metal silicide nanowires such as copper silicide have been shown to self-assemble into nanowire and nanoisland structures on the surface of silicon substrates. The self-assembly of these nanostructures occurs during reactive deposition epitaxy (RDE). It was observed that varying the surface step orientation of a sample with respect to an applied electric field had a direct influence on the length...
We present updated results of our research on the p-type silicon PERL solar cells with plated Ni/Cu/Ag or Ni/Ag contacts, Al2O3 rear passivation, and screen-printed local Al BSF. Large-area cells prepared on 156 mm commercial-grade boron-doped Cz Si wafers show maximum 21.4% conversion efficiency, and maximum 675 mV open-circuit voltage. Modules were successfully assembled by bonding inter-connect...
In this paper, thermal cycling of silicon power semiconductor dies mounted on polycrystalline diamond and aluminum nitride insulated substrates is presented. Thermal strain, stress and safety factor was analysed using ANSYS® static structural analyses tool to understand the dependence of thermal strain and stress. Polycrystalline diamond system exhibits higher thermal stress and low safety factor...
Curtaining effect and sample thickness constraints are always the key factors of limiting the use of ex-situ lift-out technique in advanced semiconductor device analysis. Over the years, in-situ lift-out technique has gradually replaced ex-situ lift-out because it offers greater advantages that can overcome the mentioned problems. A novel technique has been developed to prepare ultra-thin TEM specimens...
The effects of the presence of scallops along the sidewalls of filled (copper) and open (tungsten) TSVs are studied. The Bosch process is used in order to generate highly vertical deep trenches; however, the process results in scallops along the etched sidewalls. A model for the Bosch process is implemented in an in-house level set simulator in order to generate various TSV structures with small and...
This paper presents the first demonstration of a high-throughput die-to-panel assembly technology to form Cu interconnections without solder at temperatures below 200°C. This interconnection technology, previously established with individual single-chip packages on both organic and glass substrates, at pitches down to 30μm, is brought up to a significant manufacturable level by two major innovations:...
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