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We experimentally verify for the first time that random telegraph noise (RTN) in ultra-scaled MOSFETs is related to the inversion charge density in the channel. We then examine the merit of high mobility channel devices from the RTN prospective. This analysis strongly suggests that RTN is a serious obstacle for high mobility channel adoption.
In this work we report dense arrays of highly doped gate-all-around Si nanowire accumulation-mode nMOS-FETs with sub-5 nm cross-sections. The integration of local stressor technologies (both local oxidation and metal-gate strain) to achieve ≥ 2.5 GPa uniaxial tensile stress is reported for the first time. The deeply scaled Si nanowire shows low-field electron mobility of 332 cm2/V.s at room temperature,...
A novel method in minimizing mechanical bending stress on CMOS devices in ultra-thin chips is presented. It is shown, that the stress due to thin chip bending is reduced by glue-attaching a bare silicon chip on top of the active chip, thus shifting the neutral line to the active layer. The effect of the top chip thickness is investigated experimentally, determining the optimum thickness value for...
This paper presents an analytical model of the drain current in nanowire MOSFETs (Fig. 1). This architecture is aimed for ultra-scaled devices up to technology nodes sub-11nm and uses silicon films of a few nanometers in thickness. At these dimensions, some emerging physical phenomena can no more be neglected: short-channel effects (SCE) and quasi-ballistic transport (both due to the channel length...
We describe a method to couple the sp3d5s*-spin-orbit-coupled (SO) atomistic tight-binding (TB) model and linearized Boltzmann transport theory for the calculation of low-field mobility in Si nanowires (NWs). We consider scattering mechanisms due to phonons and surface roughness. We perform a simulation study of the low-field mobility in n-type and p-type Si NWs of diameters from 3nm to 12nm, in the...
The limiting carrier velocity concept allowing the determination of the nature of transport is used for the first time in Ge channel MOSFET. The limiting carrier velocity extracted on bulk germanium (Ge) pMOSFET is studied versus temperature. A drift-diffusion dominated transport is demonstrated despite the good transport quality of germanium devices down to 60 nm.
The aim of this paper is to compare the switching behavior of GaN switches with state of the art Si MOSFETs. Associated parameters in determining the power dissipation of a switch are initially discussed and compared between commercial GaN and Si switches. The Spice models of switches provided by the manufacturer are used to simulate a typical half-bridge DC-DC converter and analyze the switching...
The bipolar amplification and charge collection in Junctionless Double-Gate MOSFETs (JL-DGFET) submitted to heavy-ion irradiation are investigated. The transient response of JL-DGFET is compared to that of conventional devices operating in inversion mode (IM-DGFET). We show that the bipolar amplification is higher in junctionless devices than in conventional inversion-mode devices mainly due to the...
For the Synchronous DC-DC converter switching performance of low-voltage power MOSFETs, the gate-drain charge density (Qgd) is an important parameter. The so-called figure-of-merit, which is defined as the product of the specific on-resistance (Ron.sp) and Qgd is commonly used to quantify the switching performance for a specified off-state breakdown voltage (BVds). Two approaches are taken to reduce...
The 1/f noise of three different Ge channel p-type MOSFETs, epitaxially grown on silicon substrates was measured between 1 and 100 Hz. The difference between the p-MOSFETs is the thickness of the interfacial Si layer between Ge channel and gate stack that is needed to passivate the Ge channel. The gate stack consists of SiO2/HfO2/TaN/TiN layers. Noise in all structures complies with the McWorther...
Substrate transfer has been proposed as a postprocessing technology to transfer circuits with standard IC processing to an alternative substrate e.g. plastic. We demonstrate the intrinsic performances of nMOSFETs with 30 μm Si on plastic are a little degradation but the process can be controlled well. High flexibility of 30 μm Si on plastic enhances device characteristics under tensile strain on 15...
Adopting silicon capping layer is a promising method reducing the defect of interface between gate dielectric and SiGe deposition layer in the technology of manufacturing nano-scale devices and avoiding Ge atom diffusion into the gate dielectric or increasing the channel surface roughness. However, the junction leakage at refilled SiGe source/drain technology becomes worse. Through the deliberate...
In this work, we show that the 1/f noise can originate from temporal accumulation of structural variance in electronic devices. We compare results of our calculations to published data and we critically discuss the advantages and limitations relevant to the use of the spatial variations for explanation of the low-frequency noise in MOS transistors.
Embedded SiGe process technology in source/drain is an available method to do the compressive strain in PMOSFETs to increase the channel mobility. However, the fringe junction leakage close to gate electrodes, comparing that with the control group, is increased more. When the temperature effect is incorporated, this deterioration is more obvious. Through the decouple technology with feasible junction...
It has been well recognized that new device engineering is indispensable in overcoming difficulties of advanced CMOS and realizing high performance LSIs under 10 nm regime. According to the future evolution scenario of CMOS device/process technologies presented in the International Technology Roadmap for Semiconductors (ITRS) 2010 edition [1], new channel materials with enhanced carrier transport...
In this work the maximum UIS energy capability (Eas) for High-Voltage (600V-900V) Planar and SuperJunction (SJ) power MOSFETs is analyzed through experiment, TCAD simulation and analytical modeling. A new theoretical approach considering a buried heat source is presented to accurately predict Eas values in a wide range of voltage capability and load inductor values.
600V-class superjunction (SJ) MOSFETs fabricated by trench-filling process are investigated by analytical and numerical solutions with experimental results. The careful consideration on the effects of trench taper and p-column profile is given for accurate charge control. The breakdown voltage (Vb), specific on-resistance (RonAa), and gate-to-drain charge (Qgd) of 736 V, 16.4 mΩ-cm2, and 6 nC, respectively,...
We demonstrate AlGaN/GaN tunnel junction FETs (TJ-FET) featuring a metal-2DEG Schottky junction at the source. The TJ-FETs exhibit normally-off operation in an otherwise normally-on as-grown sample owing to a current controlling scheme different from the conventional FETs. The high 2DEG density in AlGaN/GaN heterostructure results in a thin tunnel barrier whose effective thickness is controlled by...
Power MOSFET designs have been moving to higher performance particularly in the medium voltage area. (60V to 300V) New designs require lower specific on-resistance (RSP) thus forcing designers to push the envelope of increasing the electric field stress on the shielding oxide, reducing the cell pitch, and increasing the epitaxial (epi) drift doping to reduce on resistance. In doing so, time dependant...
Silicon carbide (SiC) semiconductor devices for high power applications are now commercially available as discrete devices. Recently Schottky diodes are offered by both USA and Europe based companies. Active switching devices such as bipolar junction transistors (BJTs), field effect transistors (JFETs and MOSFETs) are now available on the commercial market. The interest is rapidly growing for these...
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