In this work we report dense arrays of highly doped gate-all-around Si nanowire accumulation-mode nMOS-FETs with sub-5 nm cross-sections. The integration of local stressor technologies (both local oxidation and metal-gate strain) to achieve ≥ 2.5 GPa uniaxial tensile stress is reported for the first time. The deeply scaled Si nanowire shows low-field electron mobility of 332 cm2/V.s at room temperature, 32% higher than bulk mobility at the equivalent high channel doping. The conduction mechanism as well as high temperature performance was studied based on the electrical characteristics from room temperature up to ≈400 K and a VTH drift of −1.72 mV/K, VFB drift of −3.04 mV/K and an ion impurity scattering-based mobility reduction were observed.
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