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A 4H-SiC MOSFET with breakdown voltage higher than 1200V has been successfully designed and fabricated. Numerical simulations have been performed to optimize the parameters of DMOSFET. The n-type epilayer is 10 μm thick with a doping of 6×1015 cm−3. The devices were fabricated with a floating guard ring edge termination. The drain current Id = 10 A at Vg = 20 V, corresponding to Vd = 2.0 V.
Radiation hard optical links are the backbone of read-out systems in high-energy physics experiments at CERN. The optical components have to withstand large doses of radiation and provide high data rates. Silicon photonics is currently being considered a promising technology to replace electrical and optical links in future experiments. It has already been demonstrated that integrated silicon Mach-Zehnder...
We report on vertical nanowire FET devices (VNWFETs) with a gate-all-around (GAA) configuration, which offer promising opportunities to enable further CMOS scaling and increased circuit layout efficiency. They allow up to 30% denser SRAM bitcells with improved read and write stability, smaller minimum operating voltages (Vmin), and lower standby leakage values as compared to cells built with lateral...
Capacitive Micromachined Ultrasonic Transducers (CMUTs) fabricated using Silicon-On-Insulator (SOI) wafers often have large thickness variation of the flexible plate, which causes variation in both pull-in voltage and resonant frequency across the CMUT array. This work presents a bond and boron etch-stop scheme for fabricating the flexible plate of a CMUT. The proposed fabrication method enables precise...
We present an experimental study on the influence of doping concentration and surface treatment on THz emission from silicon. We used THz emission spectroscopy and measurements of the surface photovoltage to obtain information on the band bending. The emission characteristics strongly depend on the preparation and quality of the silicon surface.
Data acquisition systems in High Energy Physics (HEP) experiments rely on tens of thousands of radiation hard optical links based on high data rate, low power transmitters which also have to be able to withstand high levels of different types of radiation. Radiation hardness is one of the requirements that becomes more demanding with every new generation of experiment. Previous studies have shown...
Ion Implantation processes contribute significantly to the development of power devices. In this case not smallest scale technologies are addressed, but accurate treatment of the frontside, backside and bulk material play a crucial role to guarantee for key parameters such as highest power densities and required switching behavior. Some representative examples of the development needs of high, medium...
We present a brief summary about the use of ion implantation for photovoltaic applications in the past and present. Furthermore, we highlight how ion implantation might be used in the future within the fast moving field of silicon solar cells.
SiF4 PLAD has been systematically characterized and optimized. The correlations between the etching, deposition, retained F dose and profile as functions of the PLAD process variables including implant voltage, RF power, pressure, pulse duty cycle, and the diluting gases have been extensively investigated. It was found that PLAD process by using pure SiF4 is in an etching or RIE regime, but can be...
Advanced inductively coupled plasma techniques and surface treatments have been used to demonstrate 5 nm conformal shallow junctions at low energy with no silicon structure damage. N-type PH3 plasma-assisted doping was characterized by dopant diffusion and electrical activation with increasing wafer temperature. Plasma-assisted doping at high wafer temperature showed no structure damage even at a...
A process and experimental doping profiles for thermal Atomic Layer Deposition of boron using an AlxOy host oxide are described. Simulations for the thermal ALD of elemental phosphorus and its use are discussed for an efficient oxide doping processes. The use of recoil knock-in is illustrated by simulation. A brief summary of conformal doping approaches is included.
In this work, a sub-10 nm high-κ/metal gate (HKMG) bulk fin-type field effect transistor (FinFET) devices with symmetrical N/PMOS characteristic were fabricated by a new hybrid dopant technology of plasma immersion ion implant (PIII) with traditional ion implant. This method was demonstrated to effectively reduce contact resistance and increase driving current of 18% in FinFET device. A remarkable...
The PVD-TiN metal-gate SOI-CMOS integrated circuits including inverters and ring oscillators have successfully been fabricated on a half-inch (100)-oriented SOI wafer using the minimal-fab and mega-fab hybrid process, and their electrical characteristics have systematically been investigated. It was experimentally found that almost an ideal subthreshold slope (SS) of 67 mV/decade and an extremely...
We present a general framework for simulating interfaces using an atomistic approach based on density functional theory and non-equilibrium Green's functions. The method includes all the relevant ingredients, such as doping and an accurate value of the semiconductor band gap, required to model realistic metal-semiconductor interfaces and allows for a direct comparison between theory and experiments...
This paper introduces oblique and lateral components into interleaved junction. Analytical model to characterize the complex interleaved interfaces is proposed, achieving nearly 23% reduction on energy consumption and 50% on VπLπ compared with traditional lateral junctions.
We have demonstrated a graphene photodetector with tunable photoresponse via electrostatic doping with split local back-gates formed by heavily doped silicon for the first time. A tunable photocurrent from 0 nA to 250 nA is obtained.
Nanoscale electronic devices will require the placement of dopants in a predetermined location, namely, a single atom control to explore novel functions for future nanoelectronics. Deterministic doping method, i.e. single-ion implantation, realizes ordered arrays of single-atoms in silicon, diamond and other materials, which might provide opportunities to single-dopant transport or single-photon source...
In this paper, we have proposed a new junctionless cylindrical gate (JCG) MOSFET design which is centered on both gate material engineering and source/drain extensions. In this, an analytical model for sub-threshold slope is developed. This paper shows the effect of device parameters like the channel length, oxide thickness and silicon thickness on threshold voltage and sub-threshold slope. All the...
The formation of p-n junctions is a crucial step in the fabrication of photovoltaic devices. Standard processes such as high temperature (> 800 °C) diffusion cannot provide the shallow doped layers, with abrupt interfaces. In this study, the epitaxial-like boron-doped silicon (epi-Si) thin films as emitters of c-Si solar cells with structure of ITO/epi-Si(p+)/c-Si(n) are investigated under the...
Two-dimensional carrier distributions in phosphorus (P)-implanted emitter and P-diffused emitter were analyzed using super-higher-order scanning nonlinear dielectric microscopy (SHO-SNDM). The carrier distribution was clearly visualized and quantified using calibration sample. P-type, n-type and depletion layer was discriminated from local capacitance-voltage characterization obtained from SHO-SNDM...
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