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Close-spaced vapor transport (CSVT) uses solid precursors to deposit material at high rates and with high precursor utilization. The use of solid precursors could significantly reduce the costs associated with III–V photovoltaics, particularly if growth on Si substrates can be demonstrated. We present preliminary results of the growth of GaAs1−xPx with x ≈ 0.3 and 0.6, showing that CSVT can be used...
Epitaxial CdTe with high quality, low defect density, and high carrier concentration should in principle yield high-efficiency photovoltaic devices. However, insufficient effort has been given to explore the choice of substrate for high-efficiency epitaxial CdTe solar cells. In this paper, we use numerical simulations to investigate three crystalline substrates: silicon (Si), InSb, and CdTe itself...
ZnSiP2 is a potential optoelectronic material with possible application in lasers, LED's, photonic integrated circuits, and photovoltaics. The development of ZnSiP2 as a photovoltaic material could address the current technological challenge of implementing a monolithic top cell on silicon for tandem photovoltaics. In this work we present a detailed description of the growth of ZnSiP2 single crystals,...
Epitaxial lift-off (ELO) is a process technology that can enable substantial performance enhancement and cost reduction for epitaxially grown III–V devices. [1]–[4] In particular, GaAs-based inverted metamorphic multijunction (IMM) solar cells are an attractive technology that provides flexible, light-weight and high-efficiency solar panels for portable-power and unmanned aerial vehicle (UAV) applications...
In the recent developments in the field of III–V on Si dual-junction solar cells, low attention has been paid to optimizing the device configuration to maximize its photovoltaic performance. The few practical implementations reported heretofore have been based on III–V solar cell processing techniques. Although the fabrication of conventional Si structures is a well-known technology, certain steps...
GaAs layers were grown on 2°-off (100) GaP substrates by metal-organic vapor phase epitaxy with various intermediate buffer layer structures. GaAsP and InGaAs were used for the buffer layers, and their As/P and In/Ga ratios were altered to control their lattice constants. The crystal properties of the GaAs layers were evaluated on the basis of double-crystal X-ray diffraction rocking curves, low-temperature...
The evolution of the Si bulk minority carrier lifetime during the heteroepitaxial growth of III–V on Si multi-junction solar cell structures via metal-organic vapor phase epitaxy has been analyzed. Initially, the emitter formation produces important lifetime degradation. Nevertheless, a progressive recovery was observed during the growth of the metamorphic GaAsP/Si structure. A step-wise mechanism...
We have studied the impact of threading dislocation density (TDD) on the performance of GaAs associated with the epitaxial growth on silicon (Si) substrate in either single-junction GaAs or dual-junction two-terminal GaAs/Si solar cell devices. The performance is measured under truncated spectrum due to the presence of internally lattice matched top GaInP filter with GaAs sub-cell. It is found that...
In this paper, the expectation for SiC power devices was described, followed by historical aspects. A breakthrough in epitaxial growth has brought SiC as the most attractive material for power devices. Present device technologies were introduced. Epoch-making steps done by the author's group were pointed out for SBDs and MOSFETs. The progress of SiC unipolar (majority carrier) devices with blocking...
While contamination of BF2+ implants by double charged molybdenum has been well documented, the impact of that contamination on antimony implants has not been investigated and is the subject of this study. Many advanced power processes incorporate buried p and n regions created by implanting the substrate prior to growing the final epitaxial silicon layer. One such process is our 0.35um 80V HV CMOS...
The objective of this paper is to elucidate novel applications where the low frequency component of a background signal (haze) level of a wafer inspection tool can be used to qualitatively analyze different epitaxial processes. During initial epitaxial development cycles, a fast method of qualifying the growth runs is required. While SEM inspections can sub-sample the wafer, a semi-quantitative way...
Novel Si/SiGex-Ge multi-junction solar cell structure was proposed, and pin junction Ge solar cell was fabricated on Ge substrate by sputter epitaxy for the first time, in which growth temperature was under 360°C and growth rates was ∼2 nm/s. Internal quantum efficiency at infrared wavelength was as high as 76%, with an open circuit voltage of 0.15V.
Epitaxially grown Si and Si0.6Ge0.4 are integrated as replacement of poly-Si channel in vertical cylindrical transistors for vertical NAND memory application, in order to investigate the impact of the grain boundaries on current conduction. Epi-Si outperforms both poly-Si and Epi-SiGe channels, resulting in the best conduction, with large improvement on both sub threshold swing and transconductance...
High voltage silicon (Si) thyristors have served for the high-voltage direct current (HVDC) transmission in the past four decades, but they are reaching their physical limits for blocking voltage, and rate of change of voltage and current. It becomes difficult to implement HVDC converts with smaller volume and higher efficiency using the existing Si thyristor technology. To satisfy the stringent requirements...
SiGe epilayer is extensively used as stressor in source/drain regions in PMOS. However, it is a big challenge to form germanosilicide with low contact resistivity due to poor thermal stability at high temperature. Therefore, silicon cap deposited on SiGe is applied to reduce contact resistance. In static random access memory (SRAM) area, silicon cap profile is apt to be un-conformal due to SiGe pattern...
Both shallow junction and HKMG have been integrated into the advanced logic process. This leads to the introduction of forming gas (4% H2 in N2/H2 mixture) to replace the traditional O2-based ashing process for the sake of material loss and metal oxidization in Lightly Doped Drain ash. In this work, we focused on the high volume H2 ashing not only from the point of view of physical performance but...
FinFET device has better electrostatic performance than planar device and makes devices further scaling possible. N-type bulk FinFET process challenges such as implantation induced Fin damages, Source/Darin (S/D) epitaxy and Fin profile control were discussed. Pre-Fin anti-punch trough (APT) implantation and low beam current n-type light-doped-drain (NLDD) implantation combined with optimized post-implant...
Dual-junction solar cells formed by a GaAsP cell on a silicon bottom cell seem to be attractive candidates to materialize the long sought-for integration of III–V materials on Si for photovoltaic applications. In this study, we analyze several factors for the optimization of the bottom cell, namely, 1) the emitter formation as a result of phosphorus diffusion; 2) the growth of a high quality GaP nucleation...
We demonstrate enhanced photoluminescence from Ge/SiGe quantum wells with strain from −0.28% (compressive) to 0.25% (tensile) achieved by epitaxial growth techniques. The intensity enhancement and peak shift from photoluminescence measurements are in agreement with theoretical calculations.
We compare CMP process variants used for FEOL integration of photonic components in a SiGe BiCMOS baseline. These CMP variants are part of a process sequence yielding wafers with local SOI regions surrounded by bulk Si areas. This particular wafer structure allows one to fabricate low loss photonic devices like waveguides, couplers and modulators side by side with high-performance BiCMOS devices such...
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