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This paper outlines the approach to realize a MEMS pressure sensor suitable for meeting the stringent requirements of sensing in a downhole environment reaching 175-oC temperature and 200-MPa pressure while maintaining an accuracy of better than 0.02% for an extended measurement period of several weeks during oil and gas exploration. A few sensing structures are proposed and strategies for their optimization...
Residual stress of sol-gel derived lead-zirconatetitanate (PZT) films was investigated under modified preparation conditions to realize buckled diaphragm structures for highly sensitive ultrasonic microsensors. As the modifications of the sol-gel process, pyrolysis temperature was varied from 250°C to 400°C, and the timing of crystallization annealing was modified in the multi-coating steps; with...
In this paper, a novel petaloid hollow Cu interconnection for interposer is presented, its stress can be released by free ends face to hollow Cu interconnection center, and its fabrication process for Si substrate and glass substrate are also presented. Stress distribution and Max. stress of interposer with petaloid hollow Cu interconnection comparison with normal TSV is simulated and analyzed by...
The influence of the stress on the electro-optical performance in strained silicon waveguides is analyzed by means of simulation and experimental results. There is a strong dependency between them in the static regime although carrier effects are also observed when the applied voltage increases.
Waste heat is a widely available but little used source of power. Converting a thermal gradient into electricity is conventionally done using the Seebeck effect, but devices that use this effect are naturally inefficient. An alternate approach uses microelectromechanical systems (MEMS) to generate movement and time-varying temperature from a constant temperature gradient. Ferroelectric materials can...
Breakdown voltage instability mechanism of Trench Field Plate Power MOSFET was studied. We found that breakdown voltage (BVDSS) shifts obeyed power-law time dependence by analysis of time dependent BVDSS shifts. Furthermore, stress / suspend measurements revealed that BVdss shift repeated increase / recovery behaviors. These results were discussed by Si-H bond dissociation Reaction-Diffusion (R-D)...
Passive snubber networks are especially needed in fast switching power modules to prevent overvoltage from hard switching and to minimize electromagnetic interference [1]. In a half-bridge circuit as shown in Fig. 1 (a) dissipative RC snubber networks are beneficial over single pulse capacitors as they do not generate a resonant pole in the impedance spectrum, which can be seen in Fig. 1 (b). As only...
This paper reports direct in-situ stress measurements with microscale spatial resolution in glass using Raman spectroscopy. This new technique is used to assess the reliability of copper-plated laser-drilled through package vias (TPV) in ultra-thin bare glass interposers. Bare glass panels of 3"x3" size, with 137µm and 237µm thicknesses were fabricated with laser-drilled through-package...
Open through silicon vias are direct vertical connections between different integration levels of a chip which provide higher performances per unit area in three-dimensional integrated circuits. The reliability of such structures in integrated circuits constitutes an important issue in microelectronics. This paper deals with electromigration reliability and lifetime evaluation of open copper through...
This paper provides a nano-scale simulation model to study the UV nanoimprint lithography. Simulation of molecular dynamic is used to calculate the interfacial stress between the mold and pattern-transfer-polymer layer. Energy minimization was performed to find the equilibrium molecule configuration of the material system using the ensemble of the constant number of particles, constant-volume and...
As mobile electronics are continuously driven for compact, slim and lightweight, miniaturization of IC packaging has been a must. There are increasing Wafer Level Chip Scale and fan-in Package (WLCSP) employed in electronics to achieve the miniaturization. Since WLCSP just is the Die with solder balls attached, WLCSP has the smallest footprint and the lightest weight compare to substrate base and...
In this work, investigations on stress development in electrically conductive adhesives used as a die-attachment technology for electronic devices are presented. Three electrically conductive adhesives and two measurement techniques were used for investigations. A silicon stress chip with NiCr-thin film metallic strain-gauge structures developed in our group is used for determination of stress development...
Wafer-to-wafer 3D integration has a potential tominimize the Si thickness, which enables us to connectmultiple wafers with significantly scaled through-Si vias. Inorder to achieve this type of 3D structure, backside thinningis a key step. Conventional mechanical grinding is known asthe best way to remove bulk Si in terms of cost of ownership(CoO). However, mechanical damage such as induceddislocations...
Over the past few years, temporary bonding has spread together with the development of 3D stacked IC (SIC) technology. Maturity of the various processes has constantly improved. Early processes enabled first demonstration of circuit thinning and thin wafer debonding. Each material generation has brought a step function in the technology maturity, which is now reaching a level allowing first 3D-SIC...
In recent years, the 2.5D IC (Integrated Circuit) package with TSV (Through Silicon Vias) has become important for high-bandwidth and high-performance applications. It is well known that 2.5D technology requires significant innovation in the areas of process technology, packaging, design, thermals, and test solutions leading to several hundred new technologies in a single product. With these complex...
An ultra-thinning down to 2.6-um using 300-mm 2Gb DRAM wafer has been developed. Effects of Si thickness and Cu contamination at wafer backside in terms of DRAM yield and retention characteristics are described. Total thickness variation (TTV) after thinning was below 1.9-um within 300-mm wafer. A degradation of retention characteristics occurred after thinning down to 2.6-um while no degradation...
Modeling and controlling of warpages and layout-dependent local-deformations are challenges to overcome to realize 3D stacking of dies with through-silicon vias and micro-bumps. Dies larger than about 500 mm2 are now being used for high performance computing, and large cylindrical warpage of the die and local die surface deformations can greatly affect the yield and reliability of the stacked dies...
Measurement and simulation of the stress state in the silicon die of a wafer-level fan out package can be difficult due to the complexity of high density packaging structures and the uncertainties in material properties at the nanoscale, yet these stresses directly affect the electrical behavior of the embedded active devices due to the piezoresistive effect in silicon. In this study, the residual...
Power semiconductor devices and modules need highly efficient heat dissipation system having a chip bonding layer with high thermal conductance and reliability. Ag sintering chip-attachment has several advantages for heat dissipation. This work clarifies the thermal stress profiles under thermal cycling test by 3D multi-physics solver for double-side and single-side direct bonding structures with...
Thermal management is a key challenge for TSV (through-silicon-via) enabled integrated three-dimensional microsystem and integrated microchannel cooling is believed as a promising technology because of high inner-chip cooling efficiency. In this paper, a compatible process is presented for integrating microchannel into TSV interposer and three typical types of integrated microchannel are implemented...
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