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This paper discusses the implementation details and silicon result of a 1.6 GHz dual-core Cortex-A9 on a low power High-K Metal Gate 32 nm CMOS Bulk Process. The implementation is based on a fully synthesizable flow utilizing ARM Standard Cell and Memory IP. The completed design includes power gating and Dynamic Voltage Frequency Scaling capabilities for low static and dynamic power consumption and...
Aiming at effectively addressing the dedicated testing application issues of special-purpose communication devices, this paper devotes to some research on integrated stimulating, analyzing and testing technologies for electronic communication systems and the signals to or from the systems. An open ATS (Automatic Test System) architecture based on related technologies as SI (Synthetic Instruments)...
High mobility III-V compound semiconductors are the most attractive candidates who could provide enhanced performance for future logic applications. Even so, people still hesitate to accelerate III-V materials entering into Si CMOS world. To relieve people's concerns, the integration of thin III-V on Si and Si transistor-like technique or architecture should be demonstrated.
We describe the fabrication of radiation dosimeters utilizing fully-depleted silicon-on insulator (FDSOI) substrates, and further demonstrate the detection of various ionizing radiation types including protons, a-particles, and X-rays by the threshold voltage (Vth) changes caused by the radiation-induced charge trapped in the buried oxide. Our FDSOI dosimeter exhibits a sensitivity of ~3 mV/krad(SiO...
We demonstrate selectively-grown GaAs nano/micro structures on silicon substrates by molecular beam epitaxy. Hexagonal or rectangular shaped GaAs crystals, depending on the orientation of the silicon substrate, were formed inside the silicon-dioxide-masked nanoholes at 630°C. Clear facets, which are the low-energy {011} planes, indicate single-crystalline nature of the growth. GaAs/InAs/GaAs structure...
Nondestructive control simulation is a means of assessing the ability of methods to detect or characterize quickly and simply defects. In acoustic microscopy, the micro-characterization of the key materials used in the manufacture of electronics applications, is studying the basic parameters characterizing the mechanical properties of these materials by analyzing acoustic signatures, V (z). This last...
The design and testing challenges of High Voltage RF circuits are discussed with particular reference to a recent Solid State Power Amplifier design. Using a single Si MOSFET device, we were able to produce over 2kW of pulsed power at VHF frequencies.
The physics of instability of thin film Si solar cells is strongly dependent upon the nature of the Si, whether it is amorphous or nano(also called micro)crystalline. The amorphous phase is much more unstable than the nanocrystalline phase. The instability of the amorphous Si , which is really an alloy of Si and H, and H, is primarily due to the poor microstructure of the material. The amorphous material...
With process variability increasing in advanced processes, it becomes more challenging to diagnose or debug a low-yield problem. For finding out the root causes of a low-yield problem, currently we rely on limited process data provided by foundries or diagnosis tools and physical failure analysis (PFA). Only relying on defect diagnosis analysis and PFA is not sufficient to quickly conclude with a...
This paper describes a simple method for measuring the refractive index and absorption coefficient of silicon wafers in the Infrared (IR) wavelength range using a fiber probe. The proposed technique is applied in the wavelength range 1 to 1.7 microns. Results are compared to published models and a good agreement is obtained.
Nowadays SiGe HBTs are surpassing even the fastest III-V production devices in the high-speed orbit. In this paper a comprehensive course of action to model the power gain of High Frequency 100 nm SiGe HBT is depicted with the help of S and Y- parameters. In this effort, the issues entailed in simultaneous optimization of fmax are addressed as well as measurements of power-gain are carried out. This...
The silicon MOS transistors for VLSI have been scaled down for more than forty years in order to attain higher speed, lower power, higher integration, and lower cost. The gate length is now less than 30 nm. The silicon devices are certainly in the nanometer regime. Fig. 1 shows technology nodes and gate length according to ITRS [1]. It is predicted in the 2009 version of ITRS that the gate length...
We have carried out 3D Non-Equilibrium Green Function simulations of a junctionless gate-all-around n-type silicon nanowire transistor of 4.2 × 4.2 nm2 cross-section. We model the dopants in a fully atomistic way. The dopant distributions are randomly generated following an average doping concentration of 1020 cm-3. Elastic and inelastic Phonon scattering is considered in our simulation. Considering...
In this work, cylindrical junctionless nanowire pinch-off FETs with a circular horizontal cross-section are simulated. Advanced simulation methods based on the self consistent solution of the Poisson equation (PE) and the 6x6 k · p Schrodinger equation (SE) (for pFETs) or the effective mass SE (for nFETs) are employed allowing us to handle quantum confinement, stress/strain, and arbitrary crystallographic...
We have simulated silicon nanowire junctionless transistors with a 3 nm gate length within a Density Functional Theory (DFT) framework. We explored the response of transistors to source-drain bias, VDS, and gate voltage, Vg. Also, the effect of bulk and surface adatom in the wire cross section was evaluated.
Alkaline solution etching has been employed for the texturisation the surface of monocrystalline silicon solar cell. The paper explores the better reaction conditions of alkaline solution (NaOH, Alcohol), and studies the reflectance, uniformity, spectral response, short-circuit current and conversion efficiency of the cells fabricated using wafers textured with the methods. Surface minimal reflectance...
Analytic hierarchy process (AHP) was performed on decision-making of PV modules for very large scale photovoltaic systems using sc-Si, mc-Si, a-Si, CdTe and CIS from both economic and environmental viewpoints. The amount of module, land requirement, transportation, array support and foundation varies depending on the type of PV module because of the differences of price and efficiency. In order to...
Two different silicon nanowire (SiNW) based devices are discussed as potential ion and biological sensors. Three-dimensional TCAD simulations are used to investigate and compare the efficiency of such devices upon applying an external voltage difference of ΔVg = 50 mV. The simulation results presented in this work reveal that an n-doped shell acts as sensitivity booster for uniformly doped SiNWs....
We propose monolithic 3D-ICs based on single grain Si TFTs where transistors are fabricated inside a silicon grain. Location of the grain was controlled by the μ-Czochralski process which is based on pulsed-laser crystallization of a-Si. Two single-grain TFTs layers were monolithically stacked with electron and hole mobilities of 600 cm2/Vs and 200 cm2/Vs, respectively. Electrical properties are presented...
A silicon based THz substrate integrated waveguide (SIW) bandpass filter with a pair of antipodal linearly tapered slot Antennas (ALTSA) is designed and fabricated with MEMS process. A prototype with passband range 350GHz~370GHz is measured by using a quasi-optic measurement system. The measured data are in agreement with the simulated results, which show the filter has good selection performance...
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