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In this work, cylindrical junctionless nanowire pinch-off FETs with a circular horizontal cross-section are simulated. Advanced simulation methods based on the self consistent solution of the Poisson equation (PE) and the 6x6 k · p Schrodinger equation (SE) (for pFETs) or the effective mass SE (for nFETs) are employed allowing us to handle quantum confinement, stress/strain, and arbitrary crystallographic...
A method is developed to obtain the alloy scattering coefficients from first-principles band structure calculations. It is found that the scattering matrix can be decomposed into two additive components: a chemical part due to atomic substitution and a part due to ionic relaxation. The method is then applied to find the intra-and inter-valley electron scattering rates for substitutional carbon in...
We have simulated silicon nanowire junctionless transistors with a 3 nm gate length within a Density Functional Theory (DFT) framework. We explored the response of transistors to source-drain bias, VDS, and gate voltage, Vg. Also, the effect of bulk and surface adatom in the wire cross section was evaluated.
Analytic hierarchy process (AHP) was performed on decision-making of PV modules for very large scale photovoltaic systems using sc-Si, mc-Si, a-Si, CdTe and CIS from both economic and environmental viewpoints. The amount of module, land requirement, transportation, array support and foundation varies depending on the type of PV module because of the differences of price and efficiency. In order to...
Two different silicon nanowire (SiNW) based devices are discussed as potential ion and biological sensors. Three-dimensional TCAD simulations are used to investigate and compare the efficiency of such devices upon applying an external voltage difference of ΔVg = 50 mV. The simulation results presented in this work reveal that an n-doped shell acts as sensitivity booster for uniformly doped SiNWs....
We propose monolithic 3D-ICs based on single grain Si TFTs where transistors are fabricated inside a silicon grain. Location of the grain was controlled by the μ-Czochralski process which is based on pulsed-laser crystallization of a-Si. Two single-grain TFTs layers were monolithically stacked with electron and hole mobilities of 600 cm2/Vs and 200 cm2/Vs, respectively. Electrical properties are presented...
In many communications applications semiconductor devices operate in a pulsed mode, where rapid temperature transients are continuously experienced within the die. We proposed a novel junction-level cooling technology where a metallic phase change material (PCM) was embedded in close proximity to the active transistor channels without interfering with the device's electrical response. Here we present...
In this study, the comparison of methods of improving electro-physical properties of silicon dioxide (SiO2) by means of silicon substrates fluorination in CF4 in PECVD and RIE reactors, prior to oxide deposition, has been performed. The results proved that, in general, fluorination in RIE is superior to the fluorination in PECVD reactor. The observed effects have been referred to the obtained changes...
The improvement of solar cell efficiency requires device optimization, including the careful design of contacts and doping profiles, and the implementation of light trapping strategies. In this context, electro-optical numerical simulation is essential to analyze the physical mechanisms that limit the cell efficiency and lead to design trade-offs. In this work we discuss the calibration of the relevant...
In this work we present a three-dimensional numerical simulation technique for the study of ion permeation through ion channels embedded in silicon membranes, that can be exploited for sensor applications. The results of this work clarify how the charges embedded in the protein forming the ion channel can influence ionic conductance through silicon membrane slabs, controlling the channel conductance...
An approach is proposed to calculate parameters of solar cells in the paper, which is based on the derivation of equivalent model and some standard parameters provided by manufacturers. And the influence of variation of the solar radiation and temperature on parameters is taken into account with the additional compensation parameters. According to the comparison between theoretic computing datum and...
Current generations of high performance microprocessors feature multiple cores and micro-cores, with each supporting multiple threads implemented in hardware. Such designs routinely feature billions of transistors, and chip layout teams are frequently hard pressed for placement and routing of all the functional blocks and sub-blocks that go into the design. An additional complexity arises because...
Schottky diode structures with Ge quantum dots (QDs) have been grown by Molecular Beam Epitaxy (MBE). They have been employed to fabricate NiSi Schottky diodes with Ge dots buried below the metal-semiconductor junctions. These diodes have cut-off frequencies up to 1.1 THz (calculated from S-parameter measurements up to 110GHz). Preliminary results demonstrating the implementation of Ge QD Schottky...
In this paper, we analyze, for the first time to our best knowledge, the high-temperature perspectives of Ultra-thin body (UTB) SOI MOSFETs. High-temperature behavior of threshold voltage, subthreshold slope, transconductance maximum and on-current is analyzed in details through measurements and 2D simulations. Particular attention is paid to the effect of buried oxide (BOX) and Si film thicknesses...
While crystalline silicon FET's are the key enablers for the integrated circuit field, amorphous silicon thin film transistors are the key semiconductor of the large-area electronics field, also known as “macroelectronics.” This talk reviews the basic properties of amorphous silicon, and then outlines research trends, driven in large part by new applications. These trends include increased performance,...
This work presents a process to fabricate FinFETs in bulk silicon with advancements in critical fabrication steps such as STI trench oxide recess and adjustment of fin height. These steps are accomplished with the adoption of Siconi™ Selective Material Removal (SMR™) in the fabrication flow. FinFETs obtained with this new integration scheme were tested in a co-fabrication process flow proposed to...
Low-temperature polycrystalline-silicon thin-film transistors (LTPS TFTs) have emerged as a promising technology for applications such as low-cost sensor networks. In this paper, we propose a LTPS TFT device optimization methodology based on scaling of silicon body (Tsi) and buried oxide thickness (Tbox). The proposed approach is applicable for both digital and analog circuits. Results show that using...
Scaling issues in thermal behavior of silicon MOSFETs have been discussed for devices with typically larger than 100 nm. Cutting edge technologies of silicon devices are exploring the issues in deep nanometer length scales, where it is claimed that the conventional Fourier-based thermal model does not apply. It is also claimed that the BTE-based transport model is the theoretical tool to discuss the...
Analytical drain current expressions with self-heating effect are presented for undoped polycrystalline thin film transistors (poly-Si TFTs). Temperature dependence of threshold voltage and effective mobility is involved. The expressions are derived on the basis of a first order Taylor expansion and continuous from linear regime to saturation regime. The validity of this model is verified by available...
Al/SiO2/pp+-Si metal-insulator-semiconductor (MIS) solar cell device was simulated using a comprehensive numerical model. The semiconductor layer consists of p-type Si epitaxial layer (base) which is deposited on p+-Si(001) substrate. The doping profile in the base layer was chosen to be arbitrary with different doping gradients. The effect of doping profile in the base layer and substrate was studied...
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