The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Software Defined networks (SDNs) paradigm tries to improve the network performance, facilitating the network management and the scalability basing on open-source software and adding a new entity called controller that manages the entire network. One of the goals of the controller is taking decisions in regards to routing instead of distributing it among the network nodes, as usual. However, this field...
Twitter's data centers process billions of events per day the instant the data is generated. To achieve real-time performance, Twitter has developed Heron, a streaming engine that provides unparalleled performance at large scale. Heron has been recently open-sourced and thus is now accessible to various other organizations. In this paper, we discuss the challenges we faced when transforming Heron...
In this paper, demonstration of failure recovery mechanism was conducted employing nodes developed in Software Defined Network. SDN allows programmability inside a network by providing adaptability towards advancement variation policy usage, as vendor specific policy building confines dynamic application building. In Node failure Recover, first mechanism is Bellman Ford Algorithm (shortest path algorithm)...
Bidirectional long short-term memory (BLSTM) recurrent neural networks are powerful acoustic models in terms of recognition accuracy. When BLSTM acoustic models are used in decoding, the speech decoder needs to wait until the end of a whole sentence is reached, such that forward-propagation in the backward direction can then be performed. The nature of BLSTM acoustic models makes them inappropriate...
Optical Transport Networks (OTNs) are composedof multiple devices. The configuration of these devices is man-ually done by system operators. Besides laborious and error-prone, this configuration also limits the client customizationand configuration of the network. One way out of this lack ofcustomization is the separation of control and data planes fromthese devices. The Software Defined Networks...
This paper addresses the problem of automatic technology migration of analog IC designs. The proposed method introduces a new level of abstraction, for EDA tools addressing analog IC design, allowing a systematic and effortless adaption of a design to a new technology. The new abstraction level is based on generic cell libraries, which includes topology and testbenches descriptions for specific circuit...
Named-Data Networking (NDN) is a novel clean-slate architecture for Future Internet. It has been designed to take into account a new use of the Internet and especially accessing content for a large number of users, and it integrates several features such as in-network caching, security or multipath. As NDN relies on content names instead of host address, it cannot rely on traditional Internet routing,...
Continuous down scaling of CMOS technology in recent years has resulted in exponential increase in static power consumption which acts as a power wall for further transistor integration. One promising approach to throttle the substantial static power of Field-Programmable Gate Array (FPGAs) is to power off unused routing resources such as switch boxes, known as dark silicon. In this paper, we present...
Network virtualization is becoming a fundamental building block of future Internet architectures. Although the underlying network infrastructure needed to dynamically create and deploy custom virtual networks is rapidly taking shape ( e.g., GENI), constructing and using a virtual network is still a challenging and labor intensive task, one best left to experts. In this paper, we present the concept...
Vedic maths based multiplier is a novel and high speed multiplier. Adder is one of the main components used in this technique. Using fast adder will enhance the overall performance of the Vedic multiplier. In this work, comparative analysis is done using different adder architectures in Synopsis Design Compiler with different standard cell libraries at 32/28 nm. Various Adder topologies like Ripple...
Quality control plays a key role in approximate computing to save the energy and guarantee that the quality of the computation outcome satisfies users' requirement. Previous works proposed a hybrid architecture, composed of a classifier for error prediction and an approximate accelerator for approximate computing using well trained neural-networks. Only inputs predicted to meet the quality are executed...
Neuromorphic computing using post-CMOS technologies is gaining immense popularity due to its promising abilities to address the memory and power bottlenecks in von-Neumann computing systems. In this paper, we propose RESPARC - a reconfigurable and energy efficient architecture built-on Memristive Crossbar Arrays (MCA) for deep Spiking Neural Networks (SNNs). Prior works were primarily focused on device...
Deep Neural Networks (DNNs) have demonstrated state-of-the-art performance on a broad range of tasks involving natural language, speech, image, and video processing, and are deployed in many real world applications. However, DNNs impose significant computational challenges owing to the complexity of the networks and the amount of data they process, both of which are projected to grow in the future...
In the last decade, networks-on-chip (NoC) were proposed as a potential solution to alleviate interconnect challenges posed by bus- or crossbar-based interconnects. In this context, the principal NoC challenges have been for several years on designing reliable and efficient NoC architectures. Today, NoC have found their way on several commercial applications and products indeed, but recently they...
Several data center applications such as Hadoop and OpenStack VM provisioning utilize group communication (one-to-many or many-to-many transfers). Since these applications require reliable and stable delivery, they rely on TCP for all group communications. Even though multicast lends itself naturally to these group communication patterns, it has remained largely under-deployed in the Internet owing...
This work implements three discrete switched mode power amplifier (PA) topologies, namely inverse class-D (CMCD), push-pull class-E and inverse push-pull class-E, in a GaN-on-Si process for medium power level (5–10W) femto/pico-cells base-station applications. The designs are analyzed and compared with respect to non-idealities such as bond-wire effects and input signal duty cycle variation. These...
In recent years, Deep Convolutional Neural Network (DCNN) has become the dominant approach for almost all recognition and detection tasks and outperformed humans on certain tasks. Nevertheless, the high power consumptions and complex topologies have hindered the widespread deployment of DCNNs, particularly in wearable devices and embedded systems with limited area and power budget. This paper presents...
Built-In-Self Test (BIST) being one of the techniques which are well known for their ability of providing on-chip testability feature, attracts its usage in today's System-on-Chip (SoC) designs. With the evolution of Network-on-Chip (NoC) communication for complex SoC, the need for fault tolerant systems have increased at a speed. In an attempt to design a good BIST architecture, this paper proposes...
In this paper, we present a novel control architecture capable to deal with the constrained Load Frequency Control (LFC) problem in a distributed way and to jointly manage time-delay attacks on the communication links existing amongst power areas and a set of high level controllers located at remote sides. The starting idea consists in abstractly modeling the power grid as a leader-follower configuration...
In this paper we discuss about 3 general issues on mesh topology in “networks on chip” (NOC): Utilizing multi-level mesh for delay reduction, using route by considering the mesh topology concept, and finally an optimal model of mesh topology named “multi-level mesh topology” which is defined based on 5-layer network model is suggested. In multi-level mesh topology we can see that this architecture...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.