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In this paper, a new dual output DC-DC converter is proposed. This topology is achieved from another dual output dc-dc converter with a little change. Conventional dual output converters provide two same level voltages in the outputs; but this topology provide two different voltage levels. In this topology, one of the output voltage gain has a considerable increment. This topology, uses two switches...
This paper proposes a design to reduce the size of traditional stepped-impedance low-pass filters and a solution to the discontinuity problem encountered in the original design. In this design, the low-impedance sections of the traditional design are replaced by periodical structures with shunt elements. The structure itself features size reduction and the new characteristic impedance is made equal...
This paper presents a discrete time fully differential CMOS signal conditioning circuit for acquisition of biosignals. It is realized using switched capacitors (SC), which provides reconfigurability, high precision, high CMRR and low sensitivity to temperature and process variations. However, the SC circuit suffers from various errors like charge injection and clock feedthrough which have an impact...
This paper presents a generic model that links the compensation techniques used in two-stage amplifiers to the structures of three-stage amplifiers. Many previous designs can be derived from this model, and new three-stage amplifiers can potentially be constructed. A novel three-stage amplifier based on this generic model is proposed. Simulation results show that the proposed design outperforms many...
A more accurate steady state analysis of the zero-voltage switching quasi-resonant (ZVSQR) converter is conducted in this paper. The conversion ratio equation and the conditions to achieve zero-voltage switching (ZVS) are derived. According to the analysis, a ZVSQR converter can be designed to operate within a wider input voltage range. A ZVSQR inverted buck converter is simulated as an example to...
This paper proposes a novel method for ripple cancellation in multi-phase converters. Unlike the conventional multi-phase converter, the proposed topology can cancel the ripple irrespective of the duty ratios. The proposed topology is designed to give 3.3V output for wide supply range of 4.5 to 18V and load range of 0 to 3A in AMS 0.35um high-voltage CMOS process. Transistor level simulation results...
A low-power biomedical signal acquisition SoC is proposed for continuous health monitoring system. The SoC fully integrates a low-noise analog front-end (AFE), a current-steering low-pass filter (CSLPF), and an output buffer. A DC-rejection loop and a chopping function are added to enhance the noise performance. For processing various bio-signals, the bandwidth can be adjusted to extract the signals...
In this paper, a 13.56 MHz power-efficient CMOS active rectifier is proposed for implantable medical devices. The digital offset compensation technique automatically compensates the turn-off delay to minimize the reverse leakage current to improve the conversion efficiency. The simulation results show that the proposed rectifier achieves 92.9% PCE with wide input voltage range. The input operating...
A triple-band compact antenna fed by coplanar waveguide (CPW) suitable for indoor communication is presented in this paper. The proposed structure is the combination of a complementary split-ring resonator (CSRR) and a left-handed transmission line (LHTL). The CSRR, working in quarter-wave monopole mode, contributes the first two operating frequency bands, which are further broadened by an additional...
Capacitance and tan δ measurements are usually carried out to check the healthiness of an insulation. Measuring equipment based on different methodologies to test insulation in cables, transformer bushings etc. are available. This paper presents the development of such a measuring equipment for a high voltage (HV) laboratory of a University. The design is divided into three parts as filter unit, test...
One of the most popular issues in the power distribution is the quality improvement due to the increased usage of power electronic based loads. This paper analyse the performance of Unified Power Quality Conditioner which is the combination of Series Active Power Filter (SAPF) and Shunt/Parallel Active Power Filter (PAPF) sharing a common DC bus capacitor. A Left Shunt UPQC (LS-UPQC) configuration...
A switch-based technique has been presented for efficient inductive power transmission at large coupling distances. Unlike the conventional inductive link, in which the receiver (Rx) LC-tank is utilized as a voltage source, the proposed link switches the Rx LC-tank in a novel fashion to act as a current source. Therefore, the voltage across the load (RL) can be significantly larger than the Rx LC-tank...
This paper presents a low-power 11-bit 1-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) that uses a self-dithering technique. The LSBs is employed as a dither to improve the resolution. Compared to converters that use the conventional dithering architecture, simulation results show that the proposed self-dithering technique improve the DNL performance with simplified...
This paper presents a novel generalized topology of a multilevel inverter. The proposed topology is obtained by extending the developed H-bridge topology. The proposed topology is competent to generate the optimum number of output voltage levels by using minimum number of dc voltage sources. The topology offers reduced value of voltage stress on semiconductor power switches. Utilization of dc voltage...
The grid connectivity requirements imposed today, ask for an accurate controller design able to deal with system constraints and nonlinearities. In order to fulfill grid international standards, this paper details a Finite control set model predictive controller called FCS-MPC as part of controlling an energy conversion system. It uses a discrete time 3L-NPC inverter model (in the α-β frame) to predict...
Conventional three-phase MMC consists of six-arms, each arm is controlled to generate unipolar voltage ranging from zero to Vdc where Vdc is the input DC voltage. Each arm voltage has two components (DC and AC components). In this work, the operation of MMC with reduced number of arms (four arms only), correspondingly reduced cost is presented. This mode can be also used with the conventional three-phase...
This work presents the implementation of an 11 Bit pipelined successive approximation register ADC (PSAR) in a 65 nm technology. The proposed ADC utilizes comparator-based switch-capacitor circuits and zero-detection in order to enable fast and high linear residue amplification with at reasonable area costs. Simulation results indicate conversion rates of 4.4 MSPS and energy consumption of 48.8 fJ...
Three phase converters are favorable for high power grid connected systems. In photovoltaic (PV) application, it is possible to remove the transformer from the PV system in order to reduce size, losses, and cost; and improve the efficiency. In other hand, presence of the parasitic capacitor between the panel's metal frame and cells causes the leakage current issue. The leakage current increases current...
This paper presents the design and simulation of a two stage power management circuit implemented in 0:18μm CMOS that operates from very low voltages starting from 460mV and higher up to a maximum of 800mV. The proposed capacitive power management unit consumes very low power of 11μW @ 500mV sufficient to be operated from tiny photovoltaic cells, dimensions of few mm2. In addition to the lower power...
Mostly, the conventional neutral point clamped (NPC)multilevel inverters are implemented for odd number of levels in the output. In this paper, four level NPC inverter is implemented and compared with the nested neutral point clamped (NNPC) inverter. The NNPC inverter is a four level inverter for high power applications. This inverter is a combination of diode clamped and flying capacitor multilevel...
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