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We present an output stage design for high switching frequency DC-DC converters. The output stage comprises level-shifters, gate drivers, and power transistors. Gate drivers designed with the low voltage-swing method are evaluated against the standard full voltage-swing. Based on the simulation results, the gate drivers with the full voltage-swing results in higher power-efficiency and correspondingly,...
A new analytical model for the CMOS inverter is introduced. This model results by solving analytically the differential equation which describes the inverter operation. It uses new simplified transistor current expressions which are developed taking into account the nanoscale effects and also considering temperature as a parameter. Expressions for the output voltage are derived, which are then used...
In this project, a Flash ADC with TIQ(Threshold Inverter Quantizer) comparator and a Wallace tree encoder is described. Both DC and transient analysis report for 3 bit ADC are included. A comparison between Wallace tree and ROM encoder is included in the project illustrating how power can be reduced using Wallace tree encoder instead of ROM encoder. The design was successfully simulated for piece-wise...
This paper is about a PV system linked to the electric grid by power electronic converters. The modeling for the converters emulates the association of a DC-DC boost with a two-level power inverter in order to follow the performance of a testing commercial inverter employed on an experimental system. It is used pulse width modulation by sliding mode control associated with space vector modulation...
Dynamic circuits using n-channel multiple-input floating-gate MOS(FGMOS) transistors to realize binary and ternary logic are presented. In binary domino circuits, the n-channel FGMOS transistors are used to replace the nMOS logic block to simplify the circuit structure. By using the advantage that voltage signals are easy to be added by means of floating gate in multiple-input FGMOS transistor, a...
An approach towards a high speed current mode SAR ADC is presented. Even though SAR ADCs based on charge redistribution have been significantly improved in efficiency and operating frequency, they are still limited by the settling requirements of the switched capacitor DAC. To overcome this limitation, we propose the use of a current mode SAR ADC incorporating a current steering DAC operating at 2...
With the increasing density of transistors in advanced technology nodes, the radiation is an ongoing problem affecting the contents of memory cells. This paper presents the simulation results of radiation immunity for two different memory cell technologies: 32nm Bulk CMOS and 28nm FDSOI. The effect of Single-Event Upset (SEU) caused by the heavy ion impact with different Linear Energy Transfer characteristic...
In this paper, a novel foreground calibration technique is presented for current-steering DACs. Each current source is in parallel with a CAL DAC injecting a small correction current that corrects the mismatch and tracks the temperature variations. High matching accuracy is not only achieved at the calibration temperature, but also maintained across a wide operating temperature range from −40 °C to...
This paper analyzes and improves the performance of a hybrid memory cell consisting of a memristor and ambipolar transistors. This work extends a previous design by efficiently biasing the memristor (as controlled by the ambipolar transistors), such that no refresh operation is now required. By utilizing macroscopic models, the features of the cell are characterized for the memory operations and no...
The most fundamental computational process encountered in digital system is binary addition, to accomplish this process binary adders are used, half adder and full adders are most often used to carry out binary addition. This paper presents a comparative analysis of design of 1bit full adder using conventional techniques and new techniques, the design and simulation of 1-bit full adder is performed...
The Ultra Low-Voltage (ULV) NAND and NOR gates are presented in this paper. These gates are based on the ULV precharge inverter presented in [11]. We intend to verify the gates' logical expression of NAND and NOR. The inbound precharge logical behaviours of the gate have been previously discussed, and therefore we aim to compare these new NAND and NOR designs to traditional Domino and CMOS logic styles...
This paper presents modeling, design and analysis of a bidirectional half-bridge DC/DC converter suitable for power electronic interface between the main energy storage system and the electric traction drive in hybrid electric vehicles. A hybrid energy storage system composed of a battery unit and an ultracapacitor pack is considered. A parallel dc-linked multi-input converter with a half-bridge bidirectional...
The design of a CMOS integrator for offset voltage monitoring in implantable neural stimulation systems is presented. It reduces the risk of electrode dissolution and tissue destruction, which might arise from a residual electrode potential after unbalanced high voltage (HV) stimulation pulses. The integrator therefore requires HV robustness and low power consumption at the same time. Monitoring low...
A low-dropout regulator (LDR) using an ultra-fast error amplifier (EA) and ultra-fast unity-gain buffer (UGB) is proposed in this paper. By inserting a UGB between the EA and the inverting second stage, the non-dominant poles are pushed to high frequencies to achieve large loading capability and wide loop bandwidth with good stability. High power supply rejection (PSR) up to very high frequencies...
We have performed non-equilibrium Green's function simulation of n-type ultra-small V-groove junctionless field-effect transistors (JL-FETs) on a silicon-on-insulator substrate under the ballistic condition. We find that the ON-current is determined mainly by the gap thickness and the subthreshold swing becomes the minimum at a gap-thickness of about 0.6 nm for the gate-length of 7.2 nm.
In this paper, a new voltage controlled oscillator (VCO) in a 0.18um CMOS process is proposed, which presents a high voltage swing and low phase noise. This new method offers better specifications with respect to traditional solutions which require higher current dissipation for increasing output voltage swing. The proposed circuit is capable of extra oscillation amplitude without increasing the current...
In this paper, a low-noise amplifier (LNA) designed for the lower band of the ultra-wideband (UWB) spectrum and implemented in 0.18 μm CMOS process is presented. Post-layout simulations show a power gain (S21) of 11.18 dB with 0.8 dB value variations from 259 MHz to 5 GHz. The input and output return losses, S11 and S22, are below −10 dB from 466.4 MHz to 5.63 GHz, while reverse isolation (S12) is...
This paper describes a new sub-volt differential difference current feedback operational amplifier. A floatinggate technique is used to reduce the supply voltage requirement. Differential difference voltage can be easily obtained by using floating-gate technique. Simulation results using TSMC 0.18 μm n-well CMOS technology are given. From a 0.8 V supply, the proposed circuit consumes 20 μW of static...
In this paper, a modified structure for low-swing voltage-mode drivers in high-speed serial links is proposed. A dynamic current-driven bulk-biasing technique is applied to the driver transistors to achieve proper channel impedance termination and to minimize the transistors' sizes. Simulation results of an 8-Gb/s serial link in all process corners of a 0.13-μm CMOS technology confirm that, by using...
In this paper a new structure of current mode minmax circuit is presented. The proposed structure can detect minimum and maximum of the input current signals simultaneously. It has advantages of analog design such as 1.5 percent error in maximum amplitude and low power consumption. Hence, the proposed circuit has high precision. The proffered circuit involves 14+4 transistors using 0.18um CMOS standard...
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