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In this study, we investigate the Ron degradation in D-mode AlGaN/GaN MIS-HEMTs on a Si substrate via an accelerated step stress at different temperatures. We have observed a three-phase Ron degradation behavior, which is highly correlated with a drain bias and back gate bias. First, the Ron degradation increases till a peak value when the drain bias increases. Second, when the drain bias increases...
Modeling the negative bias temperature instability (NBTI) can optimize circuit design. Several models have been proposed and all of them can fit test data well. These models are extracted typically by fitting short accelerated stress data. Their capability to predict NBTI aging outside the test range has not been fully demonstrated. This predictive capability for long term aging under low operation...
Dual-gated graphene field-effect transistors (FETs) are subject to stress from the top and back gate oxides, as well as the contacts. This stress alters the electronic structure of graphene. We report a study on the role of different processing steps in inducing strain in the channel of graphene FETs. We use Raman analysis to study the processing-induced strain during the fabrication of dual-gated...
Positive bias temperature instability (PBTI) of tunnel thin-film transistor (TFT) with poly-Si channel film is proposed for the first time. The novel interband tunneling transport mechanism of tunnel-TFT results in special PBTI behavior. For PBTI at 75 °C with stress voltage 10 V, tunnel-TFT exhibit excellent PBTI immunity compared to conventional TFT. However, the degradation of tunnel-TFT is getting...
This work demonstrates a novel multi-stacking PNPN channel structure for nanowire junctionless transistor. With the multi-PNPN channel structure, the design of multi-stacking PNPN junctions can promote the p-type channel layer to achieve fully depleted channel, accompanied with the excellent electrical performances on a steep subthreshold swing of 77 mV/dec and a high on/off current ratio of >10...
The unprecedented technological success of the electronics industry over the last five decades have been driven by Silicon (Si) technology at the center of which resides the metal oxide semiconductor field effect transistor (MOSFET). Relentless scaling of MOSFET dimensions ensured faster and cheaper computing since more and more transistor could be packed into the same chip area.1 At the same time...
In this work, we demonstrate a new concept for realizing high threshold voltage (Vth) E-mode GaN power devices with high maximum drain current (ID, max). A gate stack ferroelectric blocking film with charge trap layer, achieved a large positive shift of Vth. The E-mode GaN MIS-HEMTs with high Vth of 6 V shows ID, max 720 mA/mm. The breakdown voltage is above 1100 V.
The industry's first 10nm low power high performance mobile SoC has been successfully ramped in production. Thanks to a thorough design-technology co-development, 10nm SoC is 16% faster, 37% smaller, and 30% lower power than its 14nm predecessor. The latest SoC features a gigabit class modem and is set to advance AR/VR, AJ, machine learning, and computing. 10nm FinFet technology scaling challenges...
Self-heating effect (SHE) has become a significant concern for device performance, variability and reliability co-optimization due to more confined layout geometry and lower-thermal-conductivity materials adopted in advanced transistor technology, which substantially impacts the integrated circuit (IC)'s design schemes. In this work, a new methodology for evaluation of SHE in both digital and analog...
We fabricated and in-depth characterized advanced planar and nanowire CMOS devices, strained by the substrate (sSOI or SiGe channel) and by the process (CESL, SiGe source/drain). We have built a novel access resistance (RACC) extraction procedure, which enables us to clearly evidence the strong impact of back-bias and strain on Racc (−21% for 4 V Vb and −53% for −1GPa stress on pMOS FDSOI). This is...
Super-steep switching is successfully demonstrated using positive feedback (PF) in fabricated diode-type 3-D NAND flash memory strings. Thanks to the PF, the subthreshold swing (SS) measured in a cell of a string during read operation is less than 1 mV/dec at turn-on voltage (Von) regardless of the polarity and the amount of the charge stored in the cell. This string has memory characteristics similar...
In this paper, the two Negative Bias Temperature Instability (NBTI) framework components are divided with interface trap generation (Δ Vit) and hole trapping in pre-existing defects (Δ Vht). The threshold voltage shift (ΔVT) contribution is verified by two divided components and studied independently. The impact of inter layer (IL) thickness is simulated under NBTI stress using technology computer-aided...
This work demonstrates the isolation integrity between gate contact and source or drain contact with the variety of source/drain extension lengths. The trend of isolation capability not only linearly followed the extension length, but related to the formation of liner spacer. As the channel width (Wfin=0.11μm) was fixed, the IGD leakage at channel lengths Lg= 0.24, 0.16, and 10μm with LSDE= 160nm...
An automatic, defect-oriented method is proposed for activating latent defects in analog and mixed-signal integrated circuits. Based on the topology modification technique, added stress transistors generate voltage stress that activates these latent defects. This contrasts with burn-in testing which uses increased temperatures as a fault activation mechanism. Moreover, this Design-for-Testability...
The objective of this work is to investigate gate oxide degradation in Lateral Double Diffused metal-oxide semiconductor (LDMOS) devices associated with Polysilicon Buffered Locos (PBL) isolation. It was found that the defects in the silicon at the edge of Polysilicon Buffered Locos resulting in severe degradation of charge-to-breakdown (Qbd) occurring at the edge of the active area silicon have been...
This paper proposes a simple and efficient method to improve hot carrier (HC) immunity of p-channel LDMOSFET without degrading typical figure of merits such as breakdown voltage BV and specific on-resistance Rsp. The superiority of a novel STI-based p-channel LDMOSFET with a hot electron cooling (HEC) layer against the conventional method to improve HC immunity (i.e. extending the p-drift length)...
The objective of this work is to investigate gate oxide degradation in Lateral Double Diffused metaloxide semiconductor (LDMOS) devices associated with Polysilicon Buffered Locos (PBL) isolation. It was found that the defects in the silicon at the edge of Polysilicon Buffered Locos resulting in severe degradation of charge-to-breakdown (Qbd) occurring at the edge of the active area silicon have been...
Exposing the feasible annealing temperature to the high-k dielectric after deposition as gate oxide is very important to increase the capability of dielectric against the leakage and the increase of high-k value. The study does not only focus on the quality of high-k dielectric, but the reliability concern. Using the voltage stress, the recovery of gate dielectric with tested samples under different...
Two unique gate oxide failure mechanisms are associated with deep trench processes for a 0.18 μm power semiconductor device. One failure mode is a “mini-LOCOS” defect, that is due to inadvertent oxidation of Si in the active area during deep trench oxidation. The other failure mode is due to slip associated with dislocations from the deep trenches. These defects are eliminated by optimizing the SiN...
CommerciaX SiC DMOSFETs were stressed at high temperatures by applying a switching bias waveform to the gate, at a frequency around 10 kHz (similar to what a standard gate driver would do in a typical operating environment). Threshold voltage was monitored in situ (without interruption of the waveform) using a fast Id-Vgs measurement during the pulse transitions. These measurements reveal significantly...
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