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Adequate coverage of small-delay defects in circuits affected by statistical process variations requires identification and sensitization of multiple paths through potential defect sites. Existing K longest path generation (KLPG) algorithms use a data structure called path store to prune the search space by restricting the number of sub-paths considered at the same time. While this restriction speeds...
A new approach to detecting and diagnosing faults in quantum circuits is introduced. In order to account for the probabilistic nature of quantum circuits, collections of test experiments, called binary tomographic tests (BTTs), are generated. A BTT can identify a fault with respect to some user-defined confidence threshold τ. We present an algorithm to generate BTTs that either detect, or ensure the...
Advance of the fabrication technology has enhanced the size and density for the NAND Flash memory but also brought new types of defects which need to be tested for the quality consideration. This work analyzes three types of physical defects for the deep nano-meter NAND Flash memory based on the circuit level simulation and proposes new categories of interference faults (IFs). Testing algorithm is...
Cyber-physical systems have become more difficult to test as hardware and software complexity grows. The increased integration between computing devices and physical phenomena demands new techniques for ensuring correct operation of devices across a broad range of operating conditions. Manual test methods, which involve test personnel, require much effort and expense and lengthen a device's time to...
In this paper, a test is developed for the Operational Transconductor (OTA). The technology used is the 90nm CMOS technology. The assumed fault model consists of six faults per transistor including the open-gate fault. It is proven that only two test values are enough to detect 34 of the possible 36 faults, i.e., a coverage of 94.4%. A Monte Carlo analysis is then performed to study the effect, on...
As we move to smaller CMOS technologies, the need for better testing techniques arises. We investigate the effectiveness of four testing techniques against resistive-open defects. The tests are applied to two adder topologies, namely the quasi-clocked adder and the bridge-style adder. The tests are done under full process variations for technologies down to 16nm. The test techniques based on dynamic...
It has become necessary to reduce power during LSI testing. Particularly, during at-speed testing, excessive power consumed during the Launch-To-Capture (LTC) cycle causes serious issues that may lead to the overkill of defect-free logic ICs. Many successful test generation approaches to reduce IR-drop and/or power supply noise during LTC for the launch-off capture (LOC) scheme have previously been...
Purpose of the paper is to analyze the physical faults and propose a testability design method for multi-valued RTD circuits based on the stuck faults analysis and stuck faults model, which takes ternary RTD (Resonant Tunneling Diode) quantizer as an example. The test model has a high testability level and low hardware cost which consists of an extra tri-valued inverter circuit and two control ports...
Pattern generation for embedded testing often consists of a phase generating random patterns and a second phase where deterministic patterns are applied. This paper presents a method which optimizes the first phase significantly and increases the defect coverage, while reducing the number of deterministic patterns required in the second phase. The method is based on the concept of pseudo-exhaustive...
This paper presents an enhanced path delay fault simulator for combinational circuits. The main objective of this work is to improve the simulation time of path delay fault testing. Our experiments consider K-longest path sets of ISCAS'85 benchmark circuits, and 10M single input change (SIC) test patterns were applied and repeated ten times in order to cover statistical variations. The experimental...
This paper proposes integrating mutation analysis into model checking to improve coverage metrics of digital circuits. In contrast to traditional mutation testing where mutant faults are generated and injected into the code description of the model, we apply a series of newly defined mutation operators directly to the model properties rather than to the model code. We claim that any mutant properties...
An effective test generation algorithm based on threshold for digital circuits is proposed in this paper. Firstly, threshold test generation model for digital circuit is constructed, acceptable faults can be distinguished from unacceptable faults by using the model. Then threshold test patterns can be generated for unacceptable faults by using mature stuck-at faults test generation algorithm. The...
This paper proposes a novel work to design reversible quantum circuits. The function of this circuit is to investigate quantum transmission integrity in the quantum communication networks. This work is to verify quantum transmission sequence of a quantum frame by using reversible quantum model. This model designs control module to derive the correlation between two quantum strings: quantum input sequence...
As feature sizes decrease, soft errors are expected to become the dominant failure mechanisms for integrated circuits. This paper discusses the challenges that design and reliability engineers will face with the manufacture and test of ICs at advanced technology nodes.
Timing analysis is a key sign-off step in the design of today's chips, but as technology advances, it becomes ever more challenging to create timing models that accurately reflect real timing-related behavior. Complex dependencies on second order phenomena, such as pattern density and stress/strain make it very difficult to develop device models and simulation tools that accurately predict the timing...
This paper presents an Oscillation Based Test (OBT) scheme applied to a Gm-C band pass filter lacking an on-chip automatic tuning system. The fact of dealing with untuned filters prevents careless application of the traditional OBT. This is because, as a consequence of the process parameters dispersion, the use of one unique and fixed reference oscillation frequency for evaluating the test results...
The 2003 North American blackout demonstrated the importance of power swing detection, blocking and tripping for the development of a wide area disturbance into a system-wide blackout.
This paper reports on the design, development and validation of an advanced prototype 2MVA generation equipment (Naval Package) for a shipboard Medium-Voltage DC integrated power system. The generation equipment is based on a ultra-high-speed 22500-rpm 12-phase alternator which feeds an AC/DC power electronics converter composed of four diode rectifiers and four IGBT choppers. The prototype realization...
The algorithm, which avoids drawbacks of conventional approaches, has been presented for not resetable lines using GTL(Global Temporal Logic). This model checking algorithm are subject to constant improvement so that the size of manageable circuits will future increased. In this paper, based on the global temporal logic that defined by forward and reverse operator, a common formal framework for test...
Time-varying factors are extremely important in both dual-axis servo turntable and Electrostatically Supported Gyro (ESG) by affecting the testing of ESG's drift model. In this paper, we model four time-varying factors, gyro case mis-alignment angle, installation error between gyro and inner ring platform, turntable base fluctuation, and null position drift of turntable's angle sensor, as a polynomial...
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