Serwis Infona wykorzystuje pliki cookies (ciasteczka). Są to wartości tekstowe, zapamiętywane przez przeglądarkę na urządzeniu użytkownika. Nasz serwis ma dostęp do tych wartości oraz wykorzystuje je do zapamiętania danych dotyczących użytkownika, takich jak np. ustawienia (typu widok ekranu, wybór języka interfejsu), zapamiętanie zalogowania. Korzystanie z serwisu Infona oznacza zgodę na zapis informacji i ich wykorzystanie dla celów korzytania z serwisu. Więcej informacji można znaleźć w Polityce prywatności oraz Regulaminie serwisu. Zamknięcie tego okienka potwierdza zapoznanie się z informacją o plikach cookies, akceptację polityki prywatności i regulaminu oraz sposobu wykorzystywania plików cookies w serwisie. Możesz zmienić ustawienia obsługi cookies w swojej przeglądarce.
This tutorial based paper provides a unique perspective for adapting today's distribution reclose schemes to modern IED (Intelligent Electronic Device) relays which continue to offer more innovative and flexible solutions. Due to the increased overhead of the IED's configuration requirements that generally accompany these solutions, it is important to structure the settings and logic in such a way...
MicroRNAs are important modulators of gene expression. There is anecdotal evidence that the abundance of some microRNAs varies in circadian or approximately daily rhythm. In this study, using publicly available data we attempt a systematic analysis of co-expression between microRNAs and their prospective mRNA targets. An advanced analysis of periodicity with the application of digital filters in phase...
Design for test is an integral part of any VLSI chip. However, for secure systems extra precautions have to be taken to prevent that the test circuitry could reveal secret information. This paper addresses secure test for Physical Unclonable Function based systems. In particular it provides the testability analysis and a secure Built-In Self-Test (BIST) solution for Fuzzy Extractor (FE) which is the...
Even though system-on-chip (SoC) testing at multiple voltage settings significantly increases test complexity, the use of a different shift frequency at each voltage setting offers parallelism that can be exploited by time-division multiplexing (TDM) to reduce test length. We show that TDM is especially effective for small-bitwidth and heavily loaded test-access mechanisms (TAMs), thereby tangibly...
Ensuring that timing constraints in a real-time system are satisfied and met is of utmost importance. There are different static analysis methods that are introduced to statically evaluate the correctness of such systems in terms of timing properties, such as schedulability analysis techniques. Regardless of the fact that some of these techniques might be too pessimistic or hard to apply in practice,...
This paper aims to develop an Open Verification Methodology (OVM) environment to support testing of memory protocol standards and verify their operation using coverage driven verification (CDV) and constrained random testing (CRT). The objective is to achieve most of the verification plan goals with less time and effort and to create reusable verification environment components. We demonstrate the...
Modern day radio-telescopes need extremely sensitive receivers combined with powerful signal processing capabilities. Rapid urbanization and proliferation of communication devices has made these telescopes vulnerable to increasingly high levels of Radio Frequency Interference (RFI). This has necessitated development of algorithms for the mitigation of the effects of RFI either in real time or during...
RPCT is one of the key design and test issues since ATE(Automatic test equipment) channel consumption is increased dramatically for SoC(System-on-Chip) development. A new efficient RPCT test method is proposed which is based on test data compression using a burst clock controller. The proposed method considers the connection of internal/external clock signals and makes the control block using the...
This paper proposes an equivalence relation that permits to compare the external behaviors of two models of the same component of an automated discrete system: a detailed model suitable to design the control of this component and a more abstract model where only the order and the durations of the operations performed by this component are considered. A first definition of the relation is given assuming...
ESD events can induce noise on the system clock which may lead to soft-errors in the portable electronic products. This paper presents measurement techniques to investigate the ESD induced clock disturbances. At first, the soft-errors due to system level ESD testing on a DUT are shown. Next, local field scanning and direct injection are performed to identify ESD sensitive areas/traces. Techniques...
In situ testing of a high speed Analog-to-Digital Converter under gamma irradiation is impractical. A special test was developed to characterize the stability of the calibration of Texas Instruments' ADC12D1600CCMLS over a Total Ionizing Dose exposure to 300 krad(Si).
An ASIC capable of performance appropriate for processor replication and Time-Triggered Gigabit Ethernet applications was needed for the Multi-Purpose Crew Vehicle (MPCV) avionics suite. Innovative test methodologies were utilized, and favorable results obtained.
Microprocessor-based protective relays are being used throughout industrial facilities and offer the benefits of extensive metering and monitoring, which include sequence components and waveform capturing. There are two types of relay testing which is performed on microprocessor-based protective relays: (1) commission testing and; (2) routine or periodic testing. Commission testing is extensive and...
This paper is mainly focused on analyzing the behavior of the output data of a CMOS latched comparator subjected to the Human Body Model (HBM) Electrostatic Discharge (ESD) test event. The importance of the comparator circuit in the applications of data transmission is illustrated. Several tests using the Cadence IC 5.3 software were carried out in order to investigate the accuracy of the output data...
Conventional ATPG tools help in detecting only the equivalence class to which a fault belongs and not the fault itself. This paper presents PinPoint, a technique that further divides the equivalence class into smaller sets based on the capture power consumed by the circuit under test in the presence of different faults in it, thus aiding in narrowing down on the fault. Applying the technique on ITC...
The complexity of multitasked applications in real-time embedded systems presents key challenges in reliability of task execution. Interactions between periodic and aperiodic tasks can incur unpredictable deviations from ideal execution times. Runtime observations can provide visibility for analyzing real-time execution behavior of vulnerable tasks and detect when such deviations may lead to system...
Identifying speed-limiting paths is crucial for design stepping in which problematic paths are fixed or optimized so as to reach higher clock rates. Recently, using at-speed scan test patterns to identify speed-limiting paths has been reported to be a robust and effective solution. In this paper, we propose a systematic approach to find suspect path expressions (SPE) that explain the observed failing...
Completely automatic generation of tests from formal executable test models of industrial size still looks like a "holy grail", in spite of significant progress in model-based testing research and tool development. Realizing this, we follow a more down-to-earth approach by assuming that, even if a test model is available, the test expert manually derives powerful test fragments and what...
Matrix-Matrix multiplication (MMM) is widely used algorithm in today's computations and researches. Many techniques exist to speed up its execution. In this paper, we analyze the performance of MMM varying matrix size in order to determine its behavior and the region where it provides the best performance. We also determine the best speedup and efficiency in parallel implementation for different CPU...
Testing of a system-on-chip (SoC) consists of a schedule of test sessions. In each session, a subset of cores of the SoC is tested such that the peak power consumption of each core as well as that of the entire SoC remain under specified limits. In this work, we assume that each test session can be assigned its own clock frequency and VDD, which are related through the critical path delay constraint...
Podaj zakres dat dla filtrowania wyświetlonych wyników. Możesz podać datę początkową, końcową lub obie daty. Daty możesz wpisać ręcznie lub wybrać za pomocą kalendarza.