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The delay dependency of digital circuits on process, voltage and temperature variations are usually compensated by using safety margins that set the limit of operating supply voltage or clock frequency. Razor enables the processor to operate beyond this safety margin through the utilization of error detection and recovery circuits. In this paper, a single chip dual ARM9 core solution, with and without...
In today's VLSI world, the designers concentrate on low power design, neglecting the test methodology. Defining low power test methodology is the need of the day. In this paper, Microcode based Asynchronous P-MBIST is implemented, measured and compared with similar feature Synchronous PMBIST. The implemented core has given Power, Area advantage of 95.44%, 23.95% respectively but with increased Timing...
This paper will present an RMS based ripple sensor for testing of fully integrated voltage regulators. A DC signal which is proportional to the input ripple amplitude is generated. Final digital pass/fail signal is obtained with a clocked comparator. The sensor can detect a peak-to-peak ripple voltage of up to 50 millivolts on the 1.2 volts supply rail and has 220 MHz bandwidth. The sensor is designed...
The micro-motion characteristics of warheads have been utilized to discriminate false warheads from true ones. To obtain accurate dimensional measurements, a multiple-input multiple-output (MIMO) radar is adopted to observe the kinetic information of the warhead. A distributed state space model (SSM) is built and the differences between the true and false warheads are characterized as different system...
Two 32nm SOI single-event upset test chips have been irradiated at LBNL and TAMU heavy ion test facilities. The test chips include unhardened and RHBD designs such as DICE, LEAP DICE, and stacking devices. SEU cross-section data are presented for the hardened and unhardened flip-flop designs across test facility, beam tune, angle of incidence, and clock frequency.
SET and SEFI characterization of the SmartFusion2 flash-based FPGA under heavy ion irradiation is presented. Functional blocks such as the PLL and Microcontroller Sub System are characterized and presented.
SmartFusion2 Flash-based Reprogrammable FPGAs are Neutron beam tested. Results confirm immunity of SEL and configuration upset with an elevated temperature approximately 95 ºC. SEU is discussed for the Fabric Logic, Global logic, SRAM, PLL and SEFI on the MSS.
Maximum-length sequences (M-sequences) are known as pseudo random numbers generated with relatively simple digital circuits. In this paper, we present a 4-bit M-sequence generator designed and fabricated using a single-flux-quantum (SFQ) logic library and a niobium integration technology. To enhance its generation rate, we have introduced a parallelization scheme where three bits are simultaneously...
In order to solve the problem of high-speed data collection and transmission of CCD (Charge Coupled Devices) picture element, a USB 3.0 based design of high-speed data channel for CCD system is introduced in this paper. Through analyzing the requirement of the data throughput of a specific high-resolution and high frame rate CCD system, we propose this USB3.0-based scheme. By means of testing the...
QCA (Quantum-dot Cellular Automata) is the promising future nanotechnology for computing. In QCA, the cells must be aligned properly at nano scales for proper functioning. Defects may occur in synthesis and deposition phase. So the defect analyses and testing cannot be ignored. This paper presents a survey on QCA basics, defect characterization and various testing aspects of QCA.
Clock jitter is a crucial factor in high speed and high performance Analog-to-Digital Converter (ADC) testing. Random clock jitter increases the noise floor in the ADC output spectrum making it difficult to obtain the true ADC Signal to Noise Ratio (SNR). Periodic Jitter generates spurs in the ADC output spectrum. Another well-known challenge is to achieve precise coherent sampling. This paper proposes...
We "naturalize" the handshake communication links of a self-timed system by assigning the capabilities of filling and draining a link and of storing its full or empty status to the link itself. This contrasts with assigning these capabilities to the joints, the modules connected by the links, as was previously done. Under naturalized communication, the differences between Micropipeline,...
Timing errors are a major threat in nanometer technology integrated circuits. Razor is a well known timing error tolerance design technique. However, its silicon area cost makes it unattractive for widespread use. In this work, we reuse the Razor topology in order to achieve low power scan testing operations and make this technique a viable solution which will serve both on-line and off-line testing...
This research describes an approach to test metastability of flip-flops with help of multiple at speed capture cycles during path delay test. K longest paths starting from a flip-flop are generated, such that a long path on one clock cycle feeds a long path on the next clock cycle, and so on. This permits the testing of flip-flop metastability and time-borrowing latches, that cannot be tested by any...
While compaction of binary test sequences for generic sequential circuits has been widely explored, the compaction of test programs for processor-based systems is still an open area of research. Test program compaction is practically important because there are several scenarios in which Software-based Self-Test (SBST) is adopted, and the size of the test program is often a critical parameter. This...
Included in the Upgrade to NSTX at Princeton University's Plasma Physics Laboratory, is the development of a Digital Coil Protection System (DCPS). This real-time system is the primary protection for the machine coils and structure of the NSTX-U vessel. A requirement for a means to thoroughly test the DCPS birthed the Digital Coil Protection System Autotester (AT). From its inception in May of 2013,...
Real-time systems are composed of subsystems that may communicate by means of interruptions. An interruption is an event that requires preemption of a resource held by an executing subsystem. This subsystem may resume its execution from the point where it stopped when interruption handling finishes its execution. Testing systems composed of interruptions is hard since interruptions may happen at different...
Clock jitter is a crucial factor in high speed and high performance application. Traditional jitter measurement method relies on precise and expensive instrumentations. This paper proposes a low cost jitter measurement and separation method. Instead of using traditional time internal analysis equipment, a simple Analog-to-Digital Converter (ADC) is used as the jitter measurement device. The clock...
We make the case that TDF timing tests, even when aggressively applied at-speed, uniquely detect mostly open defects within standard cells. The majority of these defects can also be detected at somewhat slower test speeds without the risk of unnecessary yield loss from test noise. Meanwhile, many other opens that can cause operational failures remain undetected by current LOC, and even LOS, TDF tests...
This paper describes the commissioning methodologies and roadmap for an IEC 61850-90-5 based synchrophasor system, including PMUs, PDCs, IRIG-B and IEEE 1588 GPS clocks, synchrophasor streaming protocols and historian storage. It especially addresses lessons during the commissioning of this large-scale synchrophasor system deployment.
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