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This paper proposes a method to design low-delay fractional delay (FD) filters, using the Farrow structure. The proposed method employs both linear-phase and nonlinear-phase finite-length impulse response (FIR) subfilters. This is in contrast to conventional methods that utilize only nonlinear-phase FIR subfilters. Two design cases are considered. The first case uses nonlinear-phase FIR filters in...
Effective exploitation of the application-specific parallel patterns and computation operations through their direct implementation in hardware is the base for construction of high-quality application-specific (re-)configurable application specific instruction set processors (ASIPs) and hardware accelerators for modern highly-demanding applications. Although it receives a lot of attention from the...
The need to have hardware support for decimal arithmetic is increasing in recent years because of the growth in the decimal data processing in commercial, financial and internet based applications. In this paper a new architecture for efficient Binary coded decimal (BCD) addition/subtraction is presented that can be reconfigured to perform binary addition/subtraction. The architecture is mainly designed,...
In this paper Residue Number Systems (RNS) conversion structures from Binary to RNS modulo {2n ± 3} are proposed. These structures are based on arithmetic calculations without the need for Lookup Tables as in the related art. Additionally, the required 4:2 and 3:2 Carry-Save Adders (CSA) modulo {2n ± 3} are also proposed. Experimental results obtained for an ASIC technology suggest that the presented...
Synchronous hardware can be straight forwardly modelled as a function from input and (current) state to an updated state and output. The C?aSH compiler can translate such a transition function, described in a functional language, to synthesisable VHDL. Taking a hardware-oriented viewpoint, components can then be seen as an instantiation of such atransition function. An abstraction called Arrows is...
In this work a new efficient modulo 2n+1 modified Booth multiplication algorithm for operands in the weighted representation is proposed. According to our algorithm n/2+2 partial products are derived. The resulting partial products are reduced by an inverted end around carry save adder tree to two operands, which are finally added by a diminished-1 modulo 2n+1 adder. Our design compares favorably...
Arithmetic operations in digital signal processing applications suffer from problems including propagation delay and circuit complexity. QSD number representation allows a method of fast addition/subtraction because the carry propagation chains are eliminated and hence it reduces the propagation time in comparison with common radix 2 system. Here we propose an arithmetic unit based on QSD number system...
The diminished-one representation has been proposed for RNS-based systems with moduli of the 2^n+1 forms as an encoding that is more efficient than the normal representation in the arithmetic processing units. However, its use necessitates a two-step reverse conversion, in which a diminished-to-normal conversion is first performed before the final residue-to-binary conversion resulting in performance...
Recent researches have indicated that multi-operand addition on FPGAs can be efficiently realized as the architecture consisting of a compressor tree which reduces the number of operands and a carry-propagate adder like ASIC by utilizing generalized parallel counters(GPCs). This paper addresses power and delay aware synthesis of GPC-based compressor trees. Based on the observation that dynamic power...
Given a 16-bit or 32-bit overclocked ripple-carry adder, we minimize error by allocating multiple supply voltages to the gates. We solve the error minimization problem for a fixed energy budget using a binned geometric program solution (BGPS). A solution found via BGPS outperforms the two best prior approaches, uniform voltage scaling and biased voltage scaling, reducing error by as much as a factor...
In this paper, we present constant-coefficient finite impulse response (FIR) filters design using residue number system (RNS) arithmetic. The novelty of our approach rests in an attempt to maximize the accumulated benefit of the application of RNS to the design of constant coefficient filters. To achieve this, we consider the impact of RNS on many layers: from coefficient representation and techniques...
We propose a hybrid spin-charge fabric with computation in spin domain and communication in charge domain. In nanofabrics based on non-equilibrium physical phenomenon like interference of spin waves, switching times are lower than the thermal relaxation times leading to fast multi-value logic at high fan-in without the exponential performance degradation noticeable in CMOS. While computation is much...
Reversible logic is gaining significant consideration as the potential logic design style for implementation in modern nanotechnology and quantum computing with minimal impact on physical entropy. Recent advances in reversible logic allow schemes for computer architectures using improved quantum computer algorithms. Significant contributions have been made in the literature towards the design of reversible...
Arithmetic & Logic Unit (ALU) of a processor, when used for scientific computations, will spend more time in multiplications. Wallace multipliers perform in parallel, resulting in high speed. It uses full adders and half adders in their reduction phase. Reduced Complexity Wallace multiplier will have fewer adders than normal Wallace multiplier. In both multipliers, at the final stage, Carry propagating...
In this paper a low power and low area array multiplier with carry save adder is proposed. The proposed adder eliminates the final addition stage of the multiplier than the conventional parallel array multiplier. The conventional and proposed multiplier both are synthesized with 16-T full adder. Among Transmission Gate, Transmission Function Adder, 14-T, 16-T full adder shows energy efficiency. In...
In any general purpose processor the use of conventional full precision multipliers results in increase in the power, area and computational time. So, multipliers being the basic key element of any computation unit take its own importance in decreasing the power as well as increase in the speed. Twin Precision Multipliers has flexible and reconfigurable computational units are creating a trend which...
Carry Select Adder (CSLA) is one of the fastest adders used in many data-processing processors to perform fast arithmetic functions. From the structure of the CSLA, it is clear that there is scope for reducing the area and power consumption in the CSLA. This work uses a simple and efficient transistor-level modification to significantly reduce the area and power of the CSLA. Based on this modification...
The partial products in the normal multiplier is produced from the product of multiplier and the multiplicand, when considering the partial products the middle order take more time for final addition than considering the left and right side of the partial products, So to reduce the middle order partial product delay taking the optimal adder which is having high speed, on considering the BEC-1 adders...
Double-LSB and signed-LSB have been recently proposed as efficient encodings for addition and multiplication in the modulo 2n+1 and 2n±1 channels respectively of a Residue Number System (RNS). In this paper we introduce reverse converters for two 4-moduli sets that adopt these encodings and analyze their efficiency. The theoretical and experimental results that are derived indicate that the area and...
A novel family of codes for the detection, localization and correction of unidirectional errors for DRAMs in proposed. For DRAM memories, multi-bit soft and hard errors are a growing concern, as the cell sizes continue to decrease with aggressive scaling down. As a result, the classical error detection/correction codes become less efficient to deal with multiple errors in a single word [16]. Berger...
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