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A new 1-bit full adder cell has been introduced in this paper. According to this approach body-biasing and semi domino logic both are used in a single full adder. Body-biasing technique is used to vary the threshold voltage to operate this adder at higher speed by allowing the faster gate switching. The important thing in this approach is that there is no requirement of any external circuitry for...
Reversible logic is an emerging technique of upcoming future technologies. Low heat dissipation and energy recycle principle are encouraging its demand for low power daily usage portable devices. In this paper, two reversible gates have been proposed, named as R-I gate and R-II gate, for realizing reversible combinational logic circuits. The proposed two gates can be used for realisation of basic...
In this paper, we present a performance comparison of Binary Coded Decimal (BCD) Adders on Field Programmable Gate Logic (FPGA) for functional and behavioural verification. Although it does not prove that the circuit is reversible, implementation on FPGA serves as a platform for functional verification of circuits. BCD adders are one such circuit which has gain wide research emphasis where BCD adders...
Reversible logic is an emerging technique of upcoming future technologies. Low heat dissipation and energy recycle principle are encouraging its demand for low power daily usage portable devices. In this paper, two reversible gates have been proposed, named as R-I gate and R-II gate, for realizing reversible combinational logic circuits. The proposed two gates can be used for realisation of basic...
This paper portrays the selection of hardware unit architectures to be implemented in the new LNS based on a 32bit system. The implementations of the LNS multiply and divide only require a FXP adder, while the LNS addition and subtraction function comprised of several memories, FXP adders and multipliers together with other supporting logics. Thus, in choosing the best FXP adders and multipliers,...
The most fundamental computational process encountered in digital system is binary addition, to accomplish this process binary adders are used, half adder and full adders are most often used to carry out binary addition. This paper presents a comparative analysis of design of 1bit full adder using conventional techniques and new techniques, the design and simulation of 1-bit full adder is performed...
Carry select adder is fastest adder but it required more area and power. The modern VLSI design systems are small in size and less power consumption so the modification is need in the carry select adder to achieve the reduced area and less power consumption. Two proposed works are introduced in thispaper. First method include the reduction of area and power in Carry select adder by modifying the EX-OR...
This paper describes the design and implementation of user defined fused floating-point arithmetic operations that can be used to implement Radix 2 Fast Fourier Transform (FFT) for complex numbers used in Digital Signal Processing (DSP-C) processors. The design is implemented and simulated by targeting Xilinx vertex 5 FPGA device. This paper describes the optimization of fused floating point modules...
Adders are inevitable components in digital system design and embedded applications. The performance parameters of adders play a vital role in maximizing the efficiency of these applications. The necessity of error-tolerant circuits was prefigured in the 2003 International Technology Roadmap for Semiconductors (ITRS). Earlier works that deal with error-tolerance include flagged prefix adder and fixed...
The Ex-OR and Ex-NOR gates are the basic building blocks of various digital system applications like adder, comparator, and parity generator/checker and encryption processor. This paper proposes a full swing pass transistor based Ex-OR/Ex-NOR gate which gives better driving capability, less propagation delay and low power dissipation as compared to the existing Ex-ORlEx-NOR circuits, and by modifying...
A new low power dynamic CMOS one bit full adder cell is presented. In this design technique is based on semi-domino logic. This new cell is compared with some previous proposed widely used dynamic adders as well as other conventional architectures. Objective of this work is to inspect the power, delay, power-delay-product and leakage performance of low voltage full adder cells in different CMOS logic...
This paper proposes a Low-Power, Energy Efficient 4bit Binary Coded Decimal (BCD) adder design where the conventional 4-bit BCD adder has been modified with the Clock Gated Power Gating Technique. Moreover, the concept of DVT (Dual-vth) scheme has been introduced while designing the full adder blocks to reduce the Leakage Power, as well as, to maintain the overall performance of the entire circuit...
Design methodologies such as Razor [3,4] minimize power dissipation by slowing down circuits so as to eliminate timing slacks to the point where occasional timing errors are observed. The main challenge here is the design of efficient mechanisms to detect and recover from these infrequent errors without loss of functionality. We present a design for widely used Wallace multipliers where, because of...
Filtering being one of the most important modules in signal processing paradigm, this paper presents an FPGA implementation of various window-functions using CORDIC algorithm to minimize area-delay product. The existing window-architecture uses a linear CORDIC processor in series with circular CORDIC processor, that results in a long pipeline. Firstly, we replace the linear CORDIC with multiple optimized...
In general applications such as image processing signal processing and many similar applications find most of the work is done through multipliers to execute complex instructions. We generally use low order compressors for this multiplication operations. In this proposed paper, we are using higher order compressors to execute the multiplication operation. As these compressors have less delay, low...
A new reversible Error Tolerant Adder (ETA) based on the reversible Logic is proposed. RH and RS gates are the novel reversible logic gates based on which the ETA is designed. The reversible 3×3 RH gate is derived from existing 2×2 quantum gates — CNOT, Controlled-V and Controlled-V+. The reversible 3×3 RS gate consists of the existing CNOT and Peres Quantum gates. The design of the proposed reversible...
A Wallace tree multiplier using Booth Recoder is proposed in this paper. It is an improved version of tree based Wallace tree multiplier architecture. This paper aims at additional reduction of latency and area of the Wallace tree multiplier. This is accomplished by the use of Booth algorithm and compressor adders. The coding is done in Verilog HDL and synthesized for Xilinx Virtex 6 FPGA device....
This paper presents a Reconfigurable Parallel Prefix Ling Adder. The proposed design can be partitioned to perform as one 16 bit, two 8 bit and four 4 bit adders. We also propose a new architecture for Enhanced Flagged Binary Adder (EFBA) designs which reduces the delay of operation considerably. The new adders are, therefore, modifications of conventional Reconfigurable Carry Lookahead Adder (CLA)...
Increasing demand for the mobile, low energy systems has laid emphasis on the development of low power processors. Low power design has to be incorporated into fundamental computation units, such as multipliers. The optimization of the energy-delay product in such low power multipliers will enable energy efficient computation. This study proposes a power estimation tool to analyze different array...
This paper presents architecture of CORDIC, embedded with a scaling unit that has only minimal number of adders and shifters. It can be implemented in rotation mode as well as vectoring mode. The purpose of the design is to get a scaling free CORDIC unit preserving the design of original algorithm. The proposed design has a considerable reduction in hardware when compared with other scaling free architectures...
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